ADC BIST Sliding Histogram with Register-Based DNL and INL Testing
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Solution Overview
Problem
Traditional methods for testing analog-to-digital converters (ADCs) require large memory resources and complex instrumentation, leading to inefficiencies and increased chip complexity, particularly in histogram-based linearity testing which uses unacceptably large amounts of memory and resources.
Innovation Solution
A built-in self-test (BIST) component that utilizes hardware registers and a sliding histogram technique to test ADCs without traditional memory, synchronizing with an input voltage ramp to capture all ADC output codes and calculate differential nonlinearity (DNL) and integral nonlinearity (INL) values, determining if the ADC is defective based on these calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory is used to store histogram data for ADC testing, then measurement precision is improved, but device complexity and chip space requirements increase significantly
Solution Approach 1:
The patent extracts only the essential histogram data needed for linearity testing from traditional large memory structures. By using a sliding window approach that processes ADC output codes in sequential batches and retains only recent histogram information in hardware registers, the system eliminates the need for storing complete historical data in large memory arrays, thus reducing memory resource requirements while maintaining testing accuracy.
Solution Approach 2:
The patent changes the parameter of data storage from permanent memory storage to temporary register storage with sliding window progression. By dynamically adjusting which histogram bins are retained in hardware registers based on the sliding window position and processing ADC codes sequentially, the system maintains measurement precision without requiring large fixed memory resources.
2Measurement precision
If large memory is allocated for histogram-based testing, then measurement precision is improved, but chip area increases
Solution Approach 1:
The patent segments the ADC output code range into multiple bins and processes them sequentially through a sliding window mechanism. Instead of allocating memory for all bins simultaneously, the system divides the histogram into segments that are processed in batches, with only the current window segment retained in hardware registers at any given time, thus reducing chip space while maintaining DNL and INL calculation accuracy.
Solution Approach 2:
The patent introduces a temporal dimension to the histogram processing by using a sliding window that moves through the ADC code range over time. This transforms the spatial memory requirement into a temporal processing sequence, where data flows through the system in batches and older data is discarded after processing, effectively trading time for space and reducing chip area requirements.
3Quantity of substance
If HDL memories are used to implement large memory capacity, then storage capacity is improved, but read-write efficiency deteriorates due to sequential access requirements
Solution Approach 1:
The patent implements a self-sufficient histogram processing system using hardware registers that can simultaneously read and write histogram data without external memory access. The sliding window mechanism automatically manages data flow through the system, incrementing bin counters and updating histogram data in-place within the register file, eliminating the sequential read-write bottleneck of external HDL memories and improving processing throughput.
Data Source
AI summary
A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.