ADC Bit Compensation for Comparator Metastability
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Solution Overview
Problem
Conventional analog-to-digital converters face challenges in determining comparison results when input signals are close, leading to prolonged comparison times and metastability issues.
Innovation Solution
The proposed analog-to-digital converter incorporates a sample/hold unit, digital-to-analog converter, comparing unit, and control unit with a compensating unit and successive approximation register, which compensates current and less significant bits based on an indication signal to approximate bit weights, enabling efficient comparison and feedback generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the comparator compares two very close input signals, then the comparison accuracy is improved, but the comparison time becomes excessively long
Solution Approach 1:
The patent applies preliminary action by performing bit compensation in advance based on the indication signal before the comparison result is fully determined. When the indication signal shows that the first comparison result and second comparison result are inconsistent, the compensating unit proactively compensates the current bit and less significant bits according to the first comparison result, rather than waiting for the comparison to complete naturally. This preliminary compensation resolves the metastability issue and allows the conversion to proceed without excessive delay.
Solution Approach 2:
The patent introduces an intermediary mechanism - the indication signal and compensating unit - that mediates between the conflicting requirements of accuracy and speed. The indication signal detects whether metastability is occurring, and the compensating unit acts as an intermediary that resolves the uncertainty by forcing a determination based on the first comparison result. This intermediary layer allows the system to maintain high accuracy while avoiding excessive comparison times by intervening when metastability is detected.
2Measurement precision
If the comparator extends the comparison time to determine results for close signals, then the measurement precision is improved, but the productivity of the ADC decreases
Solution Approach 1:
The compensating unit performs preliminary compensation action when the indication signal indicates metastability. By compensating the current bit and less significant bits in advance based on the first comparison result, the system resolves the comparison uncertainty without extending the overall conversion time. This preliminary action maintains measurement precision while preserving productivity by preventing conversion delays.
Solution Approach 2:
The patent changes the parameter of bit values through compensation. When metastability is detected, the compensating unit modifies the current bit and less significant bits according to the first comparison result, effectively changing the digital output parameters to reflect the resolved comparison outcome. This parameter change resolves the contradiction by providing a definitive result that maintains accuracy without requiring extended comparison time that would reduce conversion efficiency.
3Reliability
If the system compensates current bit and less significant bits when comparison result cannot be determined, then the reliability of conversion is improved, but the device complexity increases
Solution Approach 1:
The patent introduces an intermediary compensating unit and indication signal mechanism that mediates between reliability and complexity. The indication signal detects metastability conditions, and the compensating unit resolves these conditions by compensating bits based on the first comparison result. This intermediary approach improves reliability by ensuring definitive conversion results even under metastability, while the modular design of the compensating unit keeps the added complexity manageable and localized to specific circuit components.
Data Source
AI summary
An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit.