ADC Bit-Depth Switching for Low-Power Output Resolution
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Solution Overview
Problem
Conventional analog-to-digital converter (ADC) control methods for achieving low power mode are complex, time-consuming, and require re-synthesizing coefficients or increasing capacitor area, especially when transitioning between normal and low power modes.
Innovation Solution
The ADC operates in low power mode by simply reducing the number of quantizer/ADC bits, disabling unnecessary output terminals and components, while maintaining the same loop filter order and clock frequency as in normal mode, thereby simplifying the control method and reducing design efforts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the order of the loop filter is lowered to achieve low power mode, then power consumption is reduced, but the coefficients need to be re-synthesized and the design becomes complicated
Solution Approach 1:
The patent changes the parameter of quantizer resolution (number of bits) instead of changing the loop filter order. By reducing the quantizer bit depth from 16 bits to fewer bits, the ADC achieves low power mode operation while keeping the loop filter order and coefficients unchanged, thus avoiding the complexity of re-synthesis
Solution Approach 2:
The patent extracts and removes less significant bits from the quantizer output. By disabling the output of lower-order bits (e.g., keeping only MSB to MSB-5 out of 16 bits), the system reduces power consumption without affecting the stability of the feedback path, as the feedback still uses full precision
2Use of energy by moving object
If the clock frequency of the ADC is lowered to achieve low power mode, then power consumption is reduced, but large area for loop filter capacitors is needed or a mixed system is required
Solution Approach 1:
Instead of changing the clock frequency parameter, the patent changes the quantizer resolution parameter. The ADC clock frequency remains unchanged in low power mode, eliminating the need for large capacitor areas or mixed-frequency systems while still achieving power reduction through reduced quantizer bit depth
3Use of energy by moving object
If the number of quantizer bits is reduced to achieve low power mode, then power consumption is reduced and design is simplified, but the measurement precision decreases
Solution Approach 1:
The patent segments the quantizer output into two parts: feedback path and output path. The feedback path maintains full precision (all 16 bits) to ensure stability and accuracy, while the output path can be reduced to fewer bits for low power mode. This segmentation allows the system to achieve power reduction without significantly compromising overall measurement precision, as the feedback mechanism still operates with full precision
Data Source
AI summary
The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.