ADC Bit-Width Reduction Through Interpolation and Recoverable Filtering
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face challenges in adapting to evolving data processing and transmission requirements, necessitating flexible architectures that can efficiently convert analog radio frequency signals into digital signals with reduced bit-width while maintaining high performance and low noise.
Innovation Solution
The proposed solution involves an ADC circuit with an interpolator and a digital filter that increases the sampling rate and adds shaped noise in selected portions of the data spectrum, allowing for reduced bit-width output while maintaining recoverability, and a recovery circuit that filters and decimates the signal to restore the original bit-width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ADCs use reduced bit-width output to decrease device complexity and pin requirements, then manufacturing cost and device complexity are reduced, but signal precision and data quality may deteriorate
Solution Approach 1:
The patent segments the signal processing into two stages: first converting the analog signal to digital with reduced bit-width ( simplifying the ADC), then separately processing the quantization noise through filtering and cancellation stages to recover precision. This segmentation allows the system to achieve both reduced complexity and maintained precision through distributed processing.
Solution Approach 2:
The patent deliberately discards fine quantization details by using reduced bit-width conversion, then recovers the precision information through subsequent noise filtering and cancellation processing. The quantization noise that would normally be lost is captured and processed to reconstruct the original signal precision, enabling lossless compression in the time domain.
2Measurement precision
If ADCs process high-resolution data to maintain signal quality, then measurement precision is improved, but data transmission and processing requirements increase
Solution Approach 1:
The patent extracts and separates the quantization noise component from the signal using notch filtering, then processes only the noise component for cancellation. This extraction approach allows the system to work with reduced bit-width data while maintaining full precision signal quality, improving processing efficiency by focusing computational resources on the noise cancellation aspect rather than processing the entire high-resolution signal.
Solution Approach 2:
The patent changes the bit-width parameter of the ADC output from traditional high-resolution values to reduced bit-width values, while compensating for the precision loss through dynamic noise cancellation processing. This parameter change reduces data volume and processing requirements while maintaining signal fidelity through the added noise processing stage.
3Measurement precision
If ADCs increase sampling rate to improve signal accuracy, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent implements dynamic noise cancellation where the system adaptively processes quantization noise in real-time based on the actual signal characteristics. The notch filter and cancellation circuitry dynamically adjust to the quantization noise profile, allowing the use of simpler reduced bit-width ADC architecture while maintaining accuracy through adaptive processing rather than static high-resolution conversion.
Data Source
AI summary
A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width.