ADC Input Buffer Overvoltage Clamping Without Schottky Diodes

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Solution Overview

Problem

High-speed analog-to-digital converters (ADCs) in wireless communication systems are vulnerable to overvoltage, which can damage core thin-oxide devices, and existing overvoltage protection methods using external Schottky diodes reduce bandwidth and increase costs.

Innovation Solution

An overvoltage protection circuit is integrated into the input buffer of ADCs, using a combination of thin- and thick-oxide transistors and current sources to detect and clamp voltages within reliable limits, preventing damage to sensitive devices without external diodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external Schottky diodes are used for overvoltage protection, then device reliability is improved, but bandwidth is reduced and device complexity increases

Engineering Contradiction:
Improveovervoltage protectionVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates overvoltage protection functionality directly into the input buffer circuit by combining thick-oxide transistors with the buffer architecture. This merging eliminates the need for separate external Schottky diodes, thereby maintaining reliability while reducing device complexity and component count.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The input buffer circuit is designed to perform multiple functions: signal buffering and overvoltage protection. The thick-oxide transistors within the buffer serve dual purposes by providing both buffering capability and overvoltage clamping, making the circuit universal and eliminating dedicated protection components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If external Schottky diodes are used for overvoltage protection, then device reliability is improved, but bandwidth is reduced

Engineering Contradiction:
Improveovervoltage protectionVSAvoidbandwidth
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By merging overvoltage protection into the input buffer's internal architecture using thick-oxide transistors, the protection mechanism operates within the signal path without introducing external components that would limit bandwidth. This integration ensures high-speed operation is maintained while providing reliable protection.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If external Schottky diodes are used for overvoltage protection, then device reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improveovervoltage protectionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The integration of overvoltage protection functionality into the existing input buffer circuit eliminates the need for additional external Schottky diodes. This merging reduces the bill of materials (BOM) and simplifies manufacturing processes, thereby lowering production costs while maintaining protection capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The input buffer circuit is designed to provide both signal buffering and overvoltage protection functions. This multi-functionality eliminates the need for separate protection components, reducing part count and associated manufacturing costs while ensuring reliable operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10256802B1Overvoltage protection circuit
Publication Date: 2019.04.09 XILINX INC
  • US10256802B1 patent drawing
  • US10256802B1 patent drawing
  • US10256802B1 patent drawing

AI summary

In an example, an input buffer includes: first buffer circuit having an output, a first voltage control node, and a second voltage control node; a first transistor having a gate coupled to the output of the first buffer circuit, a drain, and a source; a second buffer circuit having an input coupled to a reference voltage and an output coupled to the source of the first transistor; and a first current source having a reference output coupled to the drain of the first transistor, a first output coupled to the first voltage control node of the first buffer circuit, and a second output coupled to the second voltage control node of the second buffer circuit.