Time-Interleaved ADC Buffer Preloading to Mitigate Timing Skew
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face significant performance degradation due to timing skew, especially at high input signal frequencies, which is challenging to mitigate with current technologies, given the stringent timing resolution requirements and power constraints.
Innovation Solution
The use of dummy samplers in time-interleaved ADC circuits to preload RF-buffers with the correct dynamic load impedance at transition points between ADC sub-arrays, allowing for a smooth transition and reducing timing skew, gain, and bandwidth mismatches, without the need for additional front-end track-and-hold circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved ADC architecture is used to achieve high sampling rates, then productivity is improved, but timing skew increases causing performance degradation
Solution Approach 1:
A delay compensation circuit is introduced as an intermediary component between the parallel ADC sub-arrays. This circuit receives clock signals from the clock distribution network and adjusts their timing to compensate for skew, ensuring synchronized operation of multiple ADCs without requiring additional front-end track-and-hold circuits
Solution Approach 2:
The system dynamically adjusts timing parameters by varying the delay compensation amount in each ADC sub-array based on detected timing skew. By changing the delay parameter adaptively, the system optimizes the timing alignment of parallel ADC operations to maintain measurement precision at high sampling rates
2Measurement precision
If dummy samplers are added to mitigate timing skew, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The delay compensation circuit is merged with the existing clock distribution network, sharing infrastructure and control logic. This integration approach allows timing skew compensation to be achieved without adding completely separate control systems, thereby limiting the increase in device complexity while still improving measurement precision
3Productivity
If multiple parallel ADC sub-arrays are used to achieve high sampling rates, then productivity is improved, but gain and bandwidth mismatches increase
Solution Approach 1:
A feedback mechanism is implemented where the system detects gain and bandwidth mismatches between parallel ADC sub-arrays and automatically adjusts operating parameters. This closed-loop control compensates for manufacturing variations and environmental effects, maintaining reliable operation across all sub-arrays while achieving high sampling rates
Data Source
AI summary
The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.