ADC Input Buffer Switching for Safer, Lower-Noise Conversion
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Solution Overview
Problem
Existing Analog to Digital Converters (ADCs) face inefficiencies in converting analog signals to digital due to the need for sample switches and buffer amplifiers, which result in idle states that do not fully utilize the conversion time, leading to suboptimal signal processing and potential damage from high input voltages.
Innovation Solution
An ADC comprising an input adjustment buffer stage and a sample switch that switches between a sample and hold work state to adjust and buffer the input voltage signal, allowing for efficient analog-to-digital conversion without altering the overall timing, thereby reducing noise and ensuring the sub-ADC operates within a safe voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sample switch is placed between the buffer and ADC to enable sampling, then the ADC can convert analog signals to digital signals, but the buffer enters idle states that reduce conversion efficiency
Solution Approach 1:
The buffer amplifier continuously processes input signals during both conversion phases without entering idle states. During the first conversion phase, the buffer provides signals to the first ADC. During the second conversion phase, the buffer continues to process incoming signals while the second ADC converts, eliminating wasted time and maintaining continuous useful action.
Solution Approach 2:
The ADC system is divided into two independent conversion paths: a first ADC for initial conversion and a second ADC for subsequent conversion. This segmentation allows parallel operation where the buffer serves both converters at different times, eliminating the idle period that would occur in a single-ADC system.
2Productivity
If the buffer operates continuously without idle states, then conversion efficiency improves, but the buffer may be exposed to high input voltages that could cause damage
Solution Approach 1:
An input adjustment buffer stage is introduced as an intermediary between the input signal source and the buffer amplifier. This adjustment buffer limits the input voltage to a safe range before it reaches the main buffer, protecting it from damage while allowing the buffer to operate continuously without idle states.
Solution Approach 2:
The input adjustment buffer performs preliminary voltage limiting before the signal reaches the main buffer amplifier. By pre-adjusting the input voltage to within safe operating ranges, the system enables continuous buffer operation without risking voltage-related damage.
3Device complexity
If the input voltage is directly fed to the ADC, then the conversion process is simple, but high input voltages may damage the ADC
Solution Approach 1:
An input adjustment buffer stage serves as an intermediary between the input signal and the ADC. This adjustment buffer limits the input voltage to a safe range, protecting the ADC from damage while maintaining relatively simple circuit architecture.
Solution Approach 2:
The input adjustment buffer performs preliminary voltage limiting before the signal reaches the ADC. By pre-adjusting the input voltage to within safe operating ranges, the system protects the ADC without requiring complex protection circuits.
Data Source
AI summary
An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.