Push-Pull ADC Input Buffer With Varactors for Distortion Control
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Solution Overview
Problem
Existing input buffers for analog-to-digital converters (ADCs) face challenges in maintaining signal integrity and linearity, particularly at high frequencies and varying conditions, due to signal amplitude-dependent capacitance causing frequency-dependent distortion.
Innovation Solution
The input buffer incorporates n-channel and p-channel MOS transistors in a push-pull configuration with varactors connected to their gates, which have an inverse capacitive profile to cancel out signal amplitude dependency, reducing capacitance variation and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional input buffer is used to establish a low impedance connection, then the buffer provides basic signal transfer capability, but the capacitance of the buffer varies with signal amplitude causing frequency dependent distortion
Solution Approach 1:
The patent changes the electrical parameters of the buffer by introducing varactors that modify the capacitance characteristics. The varactors are biased to provide a capacitive profile that is inverse to the signal amplitude dependency of the underlying buffer, thereby compensating for the distortion-causing capacitance variation.
Solution Approach 2:
The varactors serve as intermediary elements inserted between the input signal and the buffer amplifiers. These varactors mediate the capacitance effect by providing an opposing capacitive profile that cancels out the harmful signal amplitude dependency of the buffer's intrinsic capacitance.
2Speed
If the input buffer operates at high frequencies (multiple GHz), then the buffer meets high speed application requirements, but the signal amplitude dependency of capacitance increases causing greater distortion
Solution Approach 1:
The patent modifies the capacitance parameters of the buffer system by adding varactors with specifically designed capacitive profiles. These varactors are biased to provide frequency-dependent capacitance characteristics that counteract the increased signal amplitude dependency that occurs at high frequencies, thereby maintaining linearity across the operating frequency range.
3Device complexity
If the input buffer uses a simple topology, then the buffer is easy to implement, but the buffer exhibits significant signal amplitude dependency of capacitance
Solution Approach 1:
The patent introduces varactors as intermediary components that can be added to existing buffer topologies without fundamentally redesigning the buffer structure. These varactors provide the necessary capacitance compensation while maintaining relatively simple implementation, as they can be integrated using standard CMOS processes and biasing circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced signal amplitude dependency and frequency-dependent distortion, ensuring improved signal integrity and linearity across process, temperature, and voltage variations.
Implementation Method 1
The first varactor and the second varactor are configured to reduce a signal amplitude dependency of a capacitance of the input buffer
Data Source
AI summary
An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (Vin) and for outputting an output signal (Vout), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V21), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.