Push-Pull ADC Input Buffer With Varactors for Low-Distortion Linearity
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Solution Overview
Problem
Existing input buffers for analog-to-digital converters (ADCs) face challenges in maintaining low impedance and linearity, especially at high frequencies, leading to frequency-dependent distortion due to signal amplitude-dependent capacitance.
Innovation Solution
The implementation of a push-pull input buffer configuration using n-channel and p-channel MOS transistors, along with varactors connected to biasing voltage potentials, to reduce signal amplitude dependency of capacitance, thereby minimizing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional input buffer is used to establish low impedance connection, then the buffer can handle high frequency signals, but the capacitance becomes signal amplitude dependent causing frequency dependent distortion
Solution Approach 1:
The patent changes the electrical parameters of the buffer by introducing varactor transistors that dynamically adjust the capacitance values. The varactors modify the gate-source and gate-drain capacitances based on control voltages, transforming the buffer from having signal amplitude-dependent capacitance to having controllable, stabilized capacitance that reduces distortion while maintaining high-frequency performance
Solution Approach 2:
The patent implements feedback mechanisms where the varactor transistors continuously adjust their capacitance values in response to signal conditions. The control voltages applied to the varactors create a feedback loop that compensates for signal amplitude variations, maintaining consistent capacitance and minimizing frequency-dependent distortion throughout the signal range
2Manufacturing precision
If the input buffer capacitance is reduced to improve linearity, then distortion decreases, but the buffer's ability to maintain low impedance at high frequencies is compromised
Solution Approach 1:
The patent introduces dynamic capacitance control through varactor transistors that can adjust their capacitance values in real-time. This dynamic adjustment allows the buffer to optimize its performance characteristics - maintaining appropriate capacitance levels for low impedance at high frequencies while minimizing signal amplitude dependency to reduce distortion, achieving both goals simultaneously through active control
3Manufacturing precision
If signal amplitude dependency of capacitance is reduced to minimize distortion, then linearity improves, but the complexity of the buffer increases due to additional varactor components
Solution Approach 1:
The patent makes the varactor transistors perform multiple functions: they serve as both the active buffering elements and the capacitance control mechanism. The same transistors that provide the push-pull buffering action also function as variable capacitors through their gate-source and gate-drain capacitances, eliminating the need for separate capacitor components and reducing overall circuit complexity while achieving distortion reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal amplitude dependency of capacitance, resulting in lower distortion and improved performance across variations in process, temperature, and voltage, enhancing the input buffer's ability to handle high-frequency signals without compromising linearity.
Implementation Method 1
The first varactor and the second varactor are configured to reduce a signal amplitude dependency of a capacitance of the input buffer
Data Source
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AI summary
An input buffer (1) for an analog-to-digital converter, ADC, (2) is provided. The input buffer is configured for receiving an input signal (Vin) and for outputting an output signal (Vout), and comprises an nMOS transistor (11) and pMOS transistor (12). The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor (21) connected between a gate of the nMOS transistor and a first biasing voltage potential (V21), and a second varactor (22) connected between a gate of the pMOS transistor and a second biasing voltage potential (V22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.