ADC Calibration DAC Clocking to Relax Anti-Alias Filters
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Solution Overview
Problem
Existing ADC calibration methods require sharp anti-alias filters, which are difficult to implement on-chip due to silicon area and loss considerations, especially when operating at different sampling rates.
Innovation Solution
The calibration DAC samples at a rational fraction p/q of the ADC sampling frequency, allowing the digital processing to distinguish between aliased spectral components and signal components, thereby eliminating the need for sharp anti-alias filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the calibration DAC samples at the same frequency as the ADC, then the calibration reference signal can be easily generated, but sharp anti-alias filters are required which increase silicon area and cause losses
Solution Approach 1:
The patent changes the sampling frequency parameter of the calibration DAC from being equal to the ADC sampling frequency to being a rational fraction p/q of it. This parameter change allows the calibration reference signal to be generated at a lower frequency, which relaxes the anti-alias filter requirements and reduces the silicon area needed for implementation.
2Ease of operation
If the calibration DAC samples at the same frequency as the ADC, then the calibration process is simplified, but high-order on-chip filters are required which increase device complexity
Solution Approach 1:
By changing the sampling frequency parameter to a rational fraction p/q of the ADC frequency, the patent simplifies the calibration process while simultaneously reducing the filter order required. The lower calibration frequency naturally pushes spectral images to higher frequencies that are easier to filter, reducing device complexity.
3Ease of manufacture
If the calibration DAC samples at the same frequency as the ADC, then the reference signal generation is straightforward, but the anti-alias filter specifications become very stringent
Solution Approach 1:
The patent changes the operating frequency parameter of the calibration DAC to a rational fraction of the ADC sampling frequency. This parameter modification relaxes the anti-alias filter specifications by reducing the cutoff frequency requirements and lowering the filter order needed, making manufacturing more feasible without compromising reference signal generation quality.
4Area of stationary object
If the calibration DAC operates at a fraction of the ADC sampling frequency, then the anti-alias filter requirements are relaxed and silicon area is reduced, but the clock signal generation becomes more complex
Solution Approach 1:
The patent introduces a fractional clock generator as an intermediary device that converts the ADC sampling clock into a rational fraction frequency for the calibration DAC. While this adds a clock generation component, it enables significant reductions in anti-alias filter silicon area and complexity, representing a beneficial trade-off in the overall system design.
Data Source
AI summary
An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.