ADC Calibration Circuit for DAC Timing Error Correction
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Solution Overview
Problem
Existing ADC calibration methods fail to correct for DAC-introduced timing errors, such as inter-symbol interference (ISI) and timing mismatches, which become more significant at higher sampling frequencies, limiting noise and distortion performance.
Innovation Solution
A calibration circuit is introduced comprising an input subtraction module, a filter module, a correlation module, an integrator module, and a correction module to estimate and correct DAC timing errors using a digital filter and adjustable loop gain, capable of handling different coding schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DAC sampling frequency is increased to improve ADC performance, then conversion speed and productivity are improved, but timing errors including ISI and timing mismatches become more dominant and worsen measurement precision
Solution Approach 1:
The patent implements a feedback-based calibration system where the ADC output is fed back through a digital filter that models the error transfer function. The calibration circuit continuously monitors the output, compares it with expected values, and adjusts DAC timing parameters to minimize timing errors. This closed-loop feedback mechanism enables the system to maintain high conversion speeds while dynamically correcting timing precision degradation caused by high-frequency operation.
Solution Approach 2:
The patent changes the timing parameters of the DAC through digital calibration to compensate for timing errors. By adjusting DAC timing parameters based on measured errors and filtering characteristics, the system optimizes performance at different sampling frequencies. This parameter adjustment allows the system to maintain measurement precision across varying productivity levels.
2Measurement precision
If digital calibration is added to correct DAC errors, then measurement precision is improved, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent designs the calibration circuit to be universally applicable across different DAC configurations and coding schemes. The digital filter module can model various error transfer functions, and the calibration algorithm adapts to different DAC architectures (single-bit, multi-bit, different element counts). This universal design allows one calibration circuit to correct timing errors in diverse ADC configurations without requiring separate specialized circuits for each case, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent introduces a digital filter as an intermediary element that models the error transfer function between the DAC and ADC. This filter acts as a mediator that characterizes the timing error behavior without requiring direct modification of the DAC hardware. By using this intermediary model, the system achieves precise error correction through software/digital processing rather than complex hardware modifications, thus improving measurement precision while controlling device complexity.
3Reliability
If calibration circuit is implemented to correct timing errors, then noise and distortion performance is improved, but ease of manufacture deteriorates due to additional calibration components
Solution Approach 1:
The patent replaces potential analog calibration mechanisms with digital signal processing approaches. Instead of using complex analog circuits to correct timing errors, the system uses digital filtering and mathematical operations to model and compensate for DAC timing errors. This substitution of digital for analog/m mechanical approaches simplifies manufacturing, as digital components are easier to fabricate with standard CMOS processes and require fewer precision-matched physical components.
Data Source
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AI summary
A calibration circuit (700) for correcting timing errors introduced by a DAC (104) in a signal path of an ADC (101), the calibration circuit (700) comprising: an input subtraction module (701) configured to subtract an estimated error from an output of the ADC (101) and provide a corrected output; a filter module (704) configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module (705) configured to correlate the corrected output with an output from the filter module (704) to extract an error term (ei); an integrator module (708) configured to integrate the error term (ei) to provide an updated error coefficient (ki); and a correction module (709) configured to correlate the updated error coefficient (ki) with the output from the filter module (704) to provide the estimated error to the input subtraction module (701).