ADC Calibration Circuit for DAC Timing Error Correction
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Solution Overview
Problem
Existing ADC technologies fail to correct for DAC-introduced timing errors such as inter-symbol interference (ISI) and timing mismatches, which become more prominent at higher sampling frequencies, limiting noise and distortion performance.
Innovation Solution
A calibration circuit comprising an input subtraction module, filter module, correlation module, integrator module, and correction module to estimate and correct DAC timing errors using a digital calibration scheme, employing a filter module like a finite impulse response (FIR) filter to approximate the error transfer function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital calibration module is used to correct static mismatch errors from the DAC, then the static mismatch error is reduced, but DAC-introduced timing errors including ISI and timing mismatches remain uncorrected and become more dominant as sampling frequency increases
Solution Approach 1:
The patent implements a feedback mechanism where the ADC output is fed back through a model of the DAC timing error (FIR filter) and correlated with the original ADC output to generate an error signal. This error signal is then used to update the error coefficients, creating a closed-loop system that continuously corrects for timing errors including ISI and timing mismatches, thereby resolving the contradiction between static mismatch correction and timing error performance
Solution Approach 2:
The patent introduces an intermediary FIR filter that models the DAC timing error transfer function. This intermediary component allows the system to separately characterize and correct timing errors without interfering with the primary static mismatch correction function, enabling both correction types to coexist and resolve the performance contradiction
2Productivity
If the sampling frequency of the DAC is increased to improve signal processing performance, then the noise and distortion performance is improved, but DAC timing errors including ISI and timing mismatches become more dominant
Solution Approach 1:
The feedback loop continuously measures the actual timing errors present in the high-frequency DAC output and generates correction signals to compensate for these errors. This allows the system to operate at high sampling frequencies for improved productivity while the feedback mechanism simultaneously suppresses the harmful timing errors that would otherwise dominate at these frequencies
Solution Approach 2:
The patent converts the harmful effect of timing errors into a measurable signal by correlating the ADC output with the FIR filter output. The timing errors that would normally degrade performance are instead used to generate an error signal that drives the correction process, transforming the harmful factor into a useful measurement for improvement
3Reliability
If a calibration circuit is added to correct DAC timing errors, then timing error correction is achieved, but the device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based timing error correction mechanisms with a digital signal processing approach. By using digital correlation and FIR filtering in the calibration module, the system achieves timing error correction without requiring complex analog circuitry, thereby reducing overall device complexity while maintaining correction effectiveness
Solution Approach 2:
The calibration circuit is designed to handle multiple types of errors (static mismatch, ISI, timing mismatches) using a unified approach based on correlation and FIR filtering. This multi-functional design reduces the need for separate correction circuits for each error type, thereby minimizing the increase in device complexity while providing comprehensive error correction
Data Source
AI summary
A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.