Multi-Stage ADC Calibration for Time-Interleaving Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in design due to speed and accuracy requirements, especially for low power solutions. Time-interleaved stages used in high-speed ADCs are susceptible to errors, require tightly controlled clock skew, and introduce spurious noise due to gain and offset errors.
Innovation Solution
A multi-stage analog-to-digital converter architecture that includes a front-end multiplying digital-to-analog converter (MDAC) and an array of time-interleaved current-controlled ring oscillator (ICRO) sub-ADCs. This architecture reduces the resolution needed for additional conversion circuitry and provides efficient calibration techniques using M-bit digital values and regions of operation determined by N-bit digital values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high sample rates, then conversion speed is improved, but sampling errors and spurious noise increase
Solution Approach 1:
The patent implements a calibration mechanism that uses feedback from the digital outputs of multiple time-interleaved ADCs to detect and correct sampling errors, gain mismatches, and offset errors. The calibration circuit receives digital words from each ADC stage and adjusts calibration parameters to minimize errors introduced by the time-interleaved architecture, thereby maintaining high conversion accuracy despite the use of parallel stages for high sample rates.
2Speed
If time-interleaved stages are used to achieve high sample rates, then conversion speed is improved, but clock skew control requirements increase
Solution Approach 1:
The calibration system operates autonomously to detect and correct timing-related errors without requiring external intervention or complex manual adjustment mechanisms. The calibration circuit automatically measures sampling errors and clock skew effects from the digital outputs of the time-interleaved ADCs and applies corrective calibration parameters, enabling the system to self-correct timing issues and reducing the need for external clock skew control complexity.
3Measurement precision
If additional conversion circuitry is added to improve accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the ADC system into multiple time-interleaved stages, each handling a portion of the conversion process. By segmenting the conversion function across parallel stages with fewer bits each, the system achieves high overall resolution without requiring a single complex high-resolution converter. The calibration circuit further segments the error correction task, applying individual calibration parameters to each stage to correct errors independently, thereby managing complexity through modular organization.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.