ADC Calibration Multiplexer for Comparator Offset Compensation
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Solution Overview
Problem
The reduction in transistor gate size in submicron-scale CMOS comparators increases intrinsic offset voltage, leading to reduced accuracy in analog-to-digital converters (ADCs) due to increased standard deviation of offset voltage, affecting the ADC's ability to compare analog signals accurately.
Innovation Solution
A variable voltage source is provided through efficient encoding of a control signal that controls multiplexers to select reference voltages, calibrating the ADC by varying only one output for a one-bit change in the least significant bit (LSB) of the multiplexer control signal, thereby reducing the differential voltage change and compensating for offset voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistor gate size is reduced to submicron scale, then power consumption decreases, but offset voltage increases and ADC accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal ADC operation. A calibration circuit measures and stores offset voltage values in lookup tables during a calibration phase, then uses these pre-measured values to compensate for offset errors during actual conversion. This resolves the contradiction by preparing compensation data in advance, allowing submicron comparators to maintain accuracy despite their inherent offset voltage.
Solution Approach 2:
The patent introduces intermediary elements including calibration circuits, lookup tables, and control logic that mediate between the submicron comparator and the final ADC output. The calibration circuit acts as an intermediary that measures offset voltage, while lookup tables store compensation values, and control logic retrieves and applies appropriate compensation. This intermediary system enables submicron comparators to achieve high accuracy without increasing power consumption.
2Quantity of substance
If transistor gate size is reduced to submicron scale, then comparator input capacitance decreases, but offset voltage standard deviation increases
Solution Approach 1:
The calibration circuit performs preliminary measurement of offset voltage in each comparator during a calibration phase, storing results in lookup tables before normal operation. This preliminary action captures the random offset characteristics of each submicron comparator, enabling subsequent compensation that addresses the increased offset standard deviation inherent to small-scale devices.
Solution Approach 2:
The patent applies local quality by implementing per-comparator calibration and compensation. Each submicron comparator is individually calibrated to measure its specific offset voltage, and separate lookup tables store compensation values for each comparator. This localized approach addresses the random offset variations in each individual comparator, maintaining reliability despite the increased offset standard deviation at submicron scales.
3Measurement precision
If reference voltage is adjusted to compensate for offset voltage, then ADC accuracy improves, but control signal complexity increases
Solution Approach 1:
The patent extracts the offset voltage measurement and compensation control functions into a separate calibration circuit and control logic unit. The main ADC comparator focuses solely on analog-to-digital conversion, while the extracted calibration circuit performs offset measurement and the control logic generates appropriate control signals for the lookup tables. This separation reduces the control signal complexity burden on the main ADC while still achieving high accuracy through systematic offset compensation.
Data Source
AI summary
A method and apparatus to provide a variable voltage source for calibrating an analog-to-digital converter (ADC) by efficient decoding of a multiplexer control signal. A multiplexer efficiently decodes the multiplexer control signal to provide a variable calibration source that has a high-accuracy digital control. The multiplexer senses the multiplexer control signal and varies only one of a multiplexer first output and a multiplexer second output for a one-bit change in a least significant bit of the multiplexer control signal. Calibrating the ADC with the variable calibration source increases the accuracy of the ADC.