Time-Interleaved ADC Calibration for Time Skew Synchronization
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Solution Overview
Problem
Conventional methods for calibrating time-interleaved analog-to-digital converters to eliminate time skew errors are complex, differ from normal conversion modes, or do not completely eliminate errors, leading to inefficiencies and potential inaccuracies in digital conversion.
Innovation Solution
A method involving feeding a predefined signal to multiple analog-to-digital converters with converter-specific time delays, converting these signals into digital values, and adapting the time delays based on the digital values to synchronize sampling instants, using a buffer circuit with operational amplifier and calibration modes to manage clock signals and adapt time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital calibration of time skews is performed using adaptive digital filter, then time skew errors are eliminated, but calibration complexity and time increase
Solution Approach 1:
The patent extracts the time skew calibration function from the complex adaptive digital filter approach and implements it through a dedicated calibration signal path. A test signal is injected separately from the normal signal path, processed through the ADCs, and the output is analyzed to determine time skew without requiring complex adaptive filtering operations during calibration.
Solution Approach 2:
The patent changes the operating parameters during calibration by injecting a known test signal with specific characteristics (frequency, amplitude) that simplifies the measurement process. The calibration mode uses different signal parameters than normal operation, allowing for simpler measurement and calculation of time skew values.
2Measurement precision
If parallel operation of ADC pairs with rapidly changing input signal is used for calibration, then time skew calibration is achieved, but calibration mode differs from normal conversion mode
Solution Approach 1:
The patent designs the calibration system to be multi-functional, allowing the same ADC hardware to operate in both normal conversion mode and calibration mode without fundamental operational changes. The calibration function is added as an overlay capability that uses the existing ADC architecture while temporarily injecting a test signal.
3Measurement precision
If sampling order is modified by algorithm with random or alternative criteria, then time skew calibration is attempted, but circuit area and power consumption increase
Solution Approach 1:
The patent uses a simple, lightweight calibration approach that does not require complex algorithms or large computational resources. The calibration method uses basic signal injection and comparison techniques that can be implemented with minimal additional circuitry, avoiding the need for sophisticated processing units or large memory structures.
4Productivity
If converter-specific time delay is applied to clock signal, then sampling synchronization is achieved, but time skew errors occur without proper calibration
Solution Approach 1:
The patent implements a feedback mechanism where the output signals from multiple ADCs are monitored and compared. Based on the observed time skew in the output signals, the system adjusts the converter-specific time delays in a closed-loop manner, feeding the measurement results back to the delay control elements to achieve optimal synchronization.
Data Source
AI summary
In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.