ADC Capacitor Weight Calibration with Integer Code Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog-to-digital converters face a resolution decrease when trying to express digital codes that exceed the expected number of bits, leading to increased costs by requiring more bits, which complicates calibration and increases hardware costs.
Innovation Solution
The proposed solution involves a capacitor array with a digital logic circuit and a comparator circuit that performs calibration on capacitors using a compensation capacitor unit to adjust digital codes to be integers expressed by the available bits, maintaining effective number of bits (ENOB) without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of bits of the analog to digital converter is increased to express digital codes beyond expected resolution, then the digital code expression capability is improved, but the hardware cost and device complexity increase
Solution Approach 1:
The patent performs capacitor weight calibration before the actual A/D conversion process. By pre-calibrating the capacitor weights and adjusting them to match ideal binary-weighted values, the system ensures that the existing bit resolution can accurately represent digital codes without needing additional bits, thus maintaining adaptability while avoiding increased hardware complexity
Solution Approach 2:
The patent adjusts the physical parameters of the capacitor array by selectively adding or removing compensation capacitors during calibration. This changes the actual capacitance values to match ideal weighted values, enabling the converter to accurately express digital codes within the existing bit range without requiring increased resolution or additional hardware
2Measurement precision
If calibration mechanisms are employed to increase resolution, then the measurement precision is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the capacitor array into multiple groups corresponding to different bit positions (MSB to LSB). Each group can be independently calibrated by adjusting compensation capacitors, allowing systematic precision improvement without requiring a monolithic complex calibration mechanism. This segmented approach simplifies the overall calibration process while maintaining high resolution
Solution Approach 2:
The patent introduces compensation capacitors as intermediary elements between the main capacitor array and the output. These compensation capacitors serve as adjustable mediators that fine-tune the weight of each capacitor group during calibration, enabling precise resolution adjustment without complicating the core capacitor array structure
3Measurement precision
If the number of bits is increased to maintain effective number of bits (ENOB), then the measurement precision is preserved, but the productivity and cost efficiency decrease
Solution Approach 1:
The patent implements a self-calibration mechanism where the A/D converter automatically adjusts its own capacitor weights during an initialization or calibration phase. By using built-in compensation capacitors and comparison logic, the system self-corrects weight errors without requiring external calibration equipment or manual intervention, maintaining ENOB while improving cost efficiency and productivity
Data Source
AI summary
An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.