ADC Capacitor Reordering to Reduce INL and DNL Errors
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Solution Overview
Problem
Analog-to-digital converters (ADCs) suffer from differential nonlinearity (DNL) and integral nonlinearity (INL) errors due to manufacturing-related issues, leading to a non-linear relationship between analog input and digital output codes, which affects the accuracy of the conversion process.
Innovation Solution
Measuring INL errors during production and programming the MSB capacitor array to reorder the capacitors based on these errors, thereby configuring the switch matrix to minimize the accumulation of DNL errors and reduce maximum INL errors, ensuring a more accurate conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitors are arranged in binary-weighted order in the MSB capacitor array, then the ADC can achieve high conversion speed and simple control logic, but manufacturing variations cause DNL and INL errors that degrade conversion accuracy
Solution Approach 1:
The patent applies preliminary action by measuring the actual capacitance values of all capacitors during manufacturing and using these measurements to determine an optimized ordering sequence before the ADC enters production use. This pre-characterization allows the system to compensate for manufacturing variations without affecting conversion speed, as the reordering is done once during setup rather than during each conversion operation.
Solution Approach 2:
The patent changes the ordering parameter of the capacitor array from fixed binary-weighted positions to a dynamically determined sequence based on measured capacitance values. By changing how capacitors are ordered (the arrangement parameter) rather than changing the capacitors themselves, the system maintains the same hardware components while optimizing their sequence to minimize INL and DNL errors, thereby improving accuracy without sacrificing conversion speed.
2Manufacturing precision
If capacitors are reordered based on measured INL errors to minimize accumulation of DNL errors, then conversion accuracy is improved, but additional measurement and programming steps increase production complexity
Solution Approach 1:
The patent applies self-service by having the ADC measure its own capacitor characteristics during a built-in test mode and automatically generate the optimized ordering sequence without requiring external test equipment or manual intervention. The device uses its internal resources (power, logic, capacitors themselves) to characterize and reorder its components, eliminating the need for complex external measurement setups and reducing production complexity while still achieving improved accuracy.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.