ADC Capacitor Reordering to Minimize INL Error Accumulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Analog-to-digital converters (ADCs) suffer from differential nonlinearity (DNL) and integral nonlinearity (INL) errors due to manufacturing tolerances in capacitors, leading to a non-linear relationship between analog input and digital output codes, which affects the accuracy of conversion.
Innovation Solution
Measuring INL errors during production and reordering the MSB capacitors based on these errors to minimize the accumulation of DNL errors, thereby configuring the switch matrix to reduce maximum INL error through programming data stored in non-volatile storage for use during power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor ordering is not optimized, then manufacturing process is simple, but INL error accumulation is large
Solution Approach 1:
The patent applies preliminary action by measuring and characterizing capacitor DNL errors during manufacturing, then pre-calculating and storing the optimal capacitor ordering sequence in a lookup table before the ADC is put into service. This allows the system to achieve reduced INL error accumulation without adding real-time computational complexity during conversion operations.
Solution Approach 2:
The patent changes the ordering parameter of capacitors based on their measured DNL characteristics. By reordering capacitors from their default sequential arrangement to an optimized sequence that alternates between positive and negative DNL capacitors, the system transforms the static capacitor array into a dynamically optimized configuration that minimizes error propagation.
2Measurement precision
If capacitor ordering is optimized to reduce INL error, then conversion accuracy improves, but measurement and programming complexity increases
Solution Approach 1:
The patent replaces complex real-time error calculation and capacitor reordering mechanisms with a pre-computed lookup table stored in non-volatile memory. Instead of performing complex measurements and calculations during ADC operation, the system uses a simple memory lookup and switching mechanism to apply the pre-determined optimal capacitor sequence, significantly reducing measurement and programming difficulty.
3Ease of operation
If MSB capacitors are used in default order, then device operation is simple, but DNL errors accumulate consecutively
Solution Approach 1:
The patent applies local quality by treating each capacitor individually based on its specific DNL characteristic rather than treating all capacitors uniformly. Capacitors with positive DNL errors and those with negative DNL errors are strategically positioned in alternating sequences, allowing each capacitor's unique error characteristic to be compensated by its neighbors, thereby maintaining simplicity while improving linearity.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.