ADC Capacitor Switching to Eliminate Charge Redistribution
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Solution Overview
Problem
Existing analog to digital converters face issues with voltage difference division and charge redistribution, leading to inefficiencies in sampling and comparison processes, particularly in sub-ADCs where sampling skew and charge redistribution prolong settling times.
Innovation Solution
An analog to digital converter design that operates in sampling and comparing modes, utilizing a comparator, capacitors, and a switch module to sample input and reference signals independently in sampling mode and couple capacitors in series in comparing mode, avoiding voltage division and charge redistribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sampling capacitors are connected in parallel to share charge difference, then voltage comparison can be performed, but the voltage difference is divided by 2 and settling time increases
Solution Approach 1:
Instead of connecting capacitors in parallel as in conventional designs, the patent connects the first and second capacitors in series during the comparing mode. This inversion of the connection topology prevents charge redistribution between capacitors, eliminating the voltage division effect and reducing settling time while maintaining accurate voltage difference measurement at the comparator input.
2Reliability
If extra sampling capacitors are added to sample reference signals, then sampling skew between MDAC and sub-ADC can be compensated, but device complexity and settling time increase
Solution Approach 1:
The patent makes the existing capacitors perform multiple functions: during sampling mode they store input signal voltages, and during comparing mode they are reconfigured in series to provide the voltage difference to the comparator. This multi-functionality eliminates the need for extra dedicated sampling capacitors while still achieving accurate signal comparison, thereby reducing device complexity.
3Productivity
If capacitors are reconfigured from parallel to series connection, then voltage difference division is eliminated, but switching control complexity increases
Solution Approach 1:
The patent employs periodic switching between two distinct operational modes: sampling mode where capacitors are connected in parallel to store signal voltages, and comparing mode where they are switched to series connection for voltage difference measurement. This periodic reconfiguration, controlled by timing signals, simplifies the switching control logic compared to continuous adjustment mechanisms, while achieving faster conversion speed by eliminating voltage division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates voltage difference division and charge redistribution, reducing settling time and enhancing operational efficiency by maintaining the integrity of the sampled voltage differences.
Implementation Method 1
a first capacitor C1, and a second capacitor C2... The first capacitor C1 samples a value of a first input signal SI1 and the second capacitor C2 samples a value of a first reference signal Sr1
Implementation Method 2
a comparator 201... the comparing operation for obtaining a comparing result of the voltage difference between the first input signal SI1 and the first reference signal Sr1
Data Source
AI summary
An analog to digital converter can operate in a sampling mode or in a comparing mode. The analog to digital converter comprises: a comparator; a first capacitor, comprising a first terminal coupled to a first input terminal of the comparator; a second capacitor; a first switch module; a control unit, for controlling the conductive states of the first switch module corresponding to the sampling mode or the comparing mode. The first capacitor samples a value of a first input signal and the second capacitor samples a value of a first reference signal via the first switch module in the sampling mode. The first capacitor and the second capacitor are not coupled to each other in the sampling mode. The first capacitor and the second capacitor are coupled in series via the first switch module in the comparing mode.