ADC Capacitor Weight Calibration for Offset and Linearity Correction
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Solution Overview
Problem
The linearity of analog-to-digital converters (ADCs) is degraded due to layout routing and process variations in the multi-stage capacitor array structure of digital-to-analog converters (DACs), leading to periodic nonlinear offsets and reduced accuracy in voltage conversion.
Innovation Solution
An analog-to-digital converting system with offset and bit-weighting correction mechanisms, comprising a capacitor circuit, comparator, switch circuit, control circuit, and decode circuit, which includes multiple capacitor groups and a bridge capacitor, allowing for attenuation coefficient calculation and correction of capacitance weights to minimize errors and improve linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a multi-stage capacitor array structure is used to reduce chip area and cost, then the capacitances required for MSB capacitors can be divided by z times, but layout routing and process variation create unexpected variations on each capacitor which degrades linearity and causes periodic nonlinear offset
Solution Approach 1:
The patent applies preliminary action by performing offset correction and bit-weighting calibration before the actual analog-to-digital conversion process. The system pre-characterizes each capacitor's actual capacitance value and stores correction data, which is then used to compensate for variations during normal operation, thereby eliminating the harmful effects of manufacturing variations.
Solution Approach 2:
The patent changes the parameter representation by transitioning from ideal capacitance values to actual measured capacitance values. The system determines actual capacitance weights for each capacitor and uses these corrected parameters in the conversion algorithm, thereby compensating for manufacturing variations and process deviations.
2Area of stationary object
If the capacitances of MSB capacitors are amplified by z times to save chip area, then the required capacitance values are reduced, but small errors in MSB capacitors are amplified by z times causing periodic nonlinear offset
Solution Approach 1:
The patent implements feedback by measuring the actual capacitance values of all capacitors and using this information to correct the conversion results. The system determines actual capacitance weights through calibration measurements and applies these correction factors to compensate for errors in the amplified MSB capacitor values, thereby eliminating periodic nonlinear offsets.
Solution Approach 2:
The system performs preliminary calibration to determine actual capacitance weights before normal conversion operations. This pre-characterization allows the system to compensate for manufacturing variations and error amplification effects during the actual conversion process, maintaining high accuracy despite the attenuated capacitor structure.
3Measurement precision
If offset correction and bit-weighting correction are implemented, then accuracy of voltage conversion is improved and linearity is enhanced, but the system complexity increases with additional correction mechanisms
Solution Approach 1:
The patent merges the offset correction and bit-weighting correction functions into a unified calibration and conversion system. The same capacitor array structure is used for both normal conversion and calibration measurements, and the correction processes are integrated into the overall conversion algorithm, thereby reducing the need for separate dedicated correction hardware.
Solution Approach 2:
The system performs self-calibration by using its own capacitor array to measure and characterize its internal variations. The calibration process automatically determines actual capacitance weights and generates correction factors without requiring external calibration equipment, thereby simplifying the overall system architecture while maintaining high accuracy.
Data Source
AI summary
An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.