Capacitor Array Weighting Calibration for SAR ADC Code Accuracy
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Solution Overview
Problem
Analog to digital converters face inaccuracies due to capacitor array mismatches, leading to errors in digital code generation, which existing technologies have not adequately addressed.
Innovation Solution
An analog to digital conversion apparatus and method that includes a capacitor array, comparator, control circuit, linearity calculating module, and calibration module to generate and adjust digital code output results based on linearity-related parameters, reducing errors by adjusting the capacitor-switching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a capacitor array is used in the SRA ADC to perform comparison based on switching activities, then the conversion process can be implemented, but inaccuracy of voltage levels is generated due to mismatch of the capacitor array
Solution Approach 1:
The patent applies preliminary action by performing calibration before actual conversion operations. The calibration module pre-adjusts the capacitor array weighting parameters to compensate for manufacturing mismatches, ensuring accurate voltage level comparisons during subsequent conversions without requiring perfect initial capacitor matching
Solution Approach 2:
The patent changes the weighting parameters of the capacitor array through calibration. By adjusting these parameters dynamically based on measured linearity errors, the system compensates for fixed manufacturing variations in capacitor values, transforming the static mismatched capacitors into an effectively matched array for accurate conversion
2Productivity
If capacitor switching activities are performed to generate digital codes, then conversion functionality is achieved, but errors result in false digital codes due to capacitor array mismatch
Solution Approach 1:
The patent implements feedback by measuring the actual linearity performance of the capacitor array and using this information to adjust the weighting parameters. The linearity calculating module continuously monitors conversion results and feeds this data back to the calibration module, which then refines the capacitor weighting to eliminate sources of false digital codes while maintaining fast conversion speed
Solution Approach 2:
The calibration process performs preliminary adjustment of capacitor weighting parameters before normal conversion operations begin. This pre-calibration ensures that the capacitor array is properly balanced to prevent generation of false digital codes during high-speed conversion operations
3Measurement precision
If calibration is performed to improve linearity, then measurement precision is improved, but device complexity increases due to additional modules
Solution Approach 1:
The patent merges the calibration functionality with the existing ADC structure by integrating the calibration module and linearity calculating module into the conversion pipeline. The calibration operations share the same capacitor array and comparator resources, combining measurement and adjustment functions within the existing architectural framework rather than adding completely separate calibration equipment
Data Source
AI summary
An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.