Time-Interleaved ADC Channel Randomization for Spur Suppression
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Solution Overview
Problem
The performance of time-interleaved ADCs is affected by mismatch between channels, leading to suboptimal correction effects and spurious signals that degrade the spurious-free dynamic range (SFDR) without affecting the effective number of bits (ENOB).
Innovation Solution
A circuit and method for channel randomization in time-interleaved ADCs, utilizing a pseudo-random number generator to disrupt the working sequence of channels, combined with a multi-phase clock distribution and adjustable delay modules to ensure sufficient quantization time for each channel, ensuring output data is arranged in chronological order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved structure is used to increase sampling rate, then productivity is improved, but channel mismatch causes spurious signals that worsen measurement precision
Solution Approach 1:
The patent applies channel randomization that dynamically changes the working sequence of channels based on pseudo-random numbers. Instead of a fixed time-interleaved sequence, channels are randomly selected and activated, making the system dynamic and adaptive. This resolves the contradiction by maintaining high sampling rates through multiple channels while randomizing their activation patterns to eliminate periodic spurious signals, thereby improving spurious-free dynamic range without sacrificing productivity
Solution Approach 2:
The patent changes the temporal parameter of channel activation by introducing random delays and variable timing intervals between channel switches. The working sequence is no longer fixed but varies randomly according to generated pseudo-random numbers. This parameter change transforms the deterministic time-interleaved structure into a stochastic process, eliminating the periodicity that causes spurious signals while maintaining the high sampling rate capability
2Measurement precision
If channel randomization is implemented to flatten spurs, then spurious-free dynamic range is improved, but quantization time may be insufficient without proper timing control
Solution Approach 1:
The patent incorporates timing control mechanisms that monitor and adjust the quantization process based on the random channel selection. The system uses feedback from the channel status register and timing control logic to ensure that each selected channel has sufficient quantization time before its output is processed. This feedback mechanism resolves the contradiction by allowing channel randomization to improve spurious-free dynamic range while automatically adjusting timing parameters to prevent quantization time insufficiency
3Device complexity
If fixed channel sequence is used, then timing control is simple, but mismatch between channels produces periodic spurious signals
Solution Approach 1:
The patent converts the harmful periodicity caused by fixed channel sequencing into a beneficial aperiodic random sequence. By using pseudo-random number generation to control channel selection, the system transforms the deterministic periodic spurious signals into random noise-like behavior. The channel mismatch still exists, but its effects are randomized and flattened across the frequency spectrum rather than concentrated at specific spurious frequencies, effectively converting the harm of channel mismatch into a beneficial suppression of periodic artifacts
Data Source
AI summary
A circuit for channel randomization based on time-interleaved ADC includes: a channel selection module for outputting M clock reception control signals and encoded N data reception control signals based on a main clock and a generated random number; a multi-phase clock distribution module for generating N multi-phase clocks according to a sampling main clock, redistributing the multi-phase clocks according to the clock reception control signals, and outputting M redistributed clock signals; a time-interleaved ADC module for outputting M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module for setting a delay length for the data reception control signals; and a timing distribution control module for controlling, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.