ADC Charge Accumulation Circuit for Dense In-Memory MAC Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ADC systems face challenges in size, accuracy, and power consumption when implemented in large-scale applications, particularly in analog in-memory compute systems, due to device mismatch effects and the need for high voltage.
Innovation Solution
The proposed ADC system utilizes a CMOS circuit with a capacitor to store input charge and develop a voltage proportional to it, incorporating a CMOS pre-charge circuit, a CMOS transistor for phase control, and a CMOS voltage level comparator to ensure consistent output across multiple ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ADC schemes with integrators and comparators are used, then charge measurement capability is achieved, but size and accuracy are limited when thousands of ADCs are required
Solution Approach 1:
The patent combines the capacitor, pre-charge circuit, comparator, and control logic into an integrated ADC circuit block that can be replicated. By merging these components into a unified structure with shared control signals and power rails, the design achieves thousands of ADCs in tight memory array bit-line pitches while maintaining accuracy and reducing overall complexity.
2Measurement precision
If circuits are duplicated for multiple ADCs, then charge measurement capability is maintained, but device mismatch effects reduce accuracy
Solution Approach 1:
The patent applies equipotentiality by pre-charging all capacitor plates to the same reference voltage Vref before charge accumulation. This ensures that all ADCs start from an identical electrical state, minimizing device mismatch effects. The common pre-charge circuit and reference voltage distribution network maintain equipotential conditions across thousands of replicated ADC circuits, ensuring consistent accuracy.
3Adaptability or versatility
If high voltage is used to provide headroom for circuits, then sufficient operating range is achieved, but power consumption becomes untenable
Solution Approach 1:
The patent employs dynamic voltage switching where the capacitor bottom plate voltage is changed from ground (during charge accumulation) to a switched voltage level (during resolution). This dynamic operation allows the circuit to achieve sufficient headroom during critical operations while consuming minimal power during idle phases. The CMOS transistor controls this dynamic switching, enabling high voltage headroom only when necessary for charge measurement.
4Reliability
If a common electrical node and common circuit ramp method are used, then consistency in ADC output is ensured, but circuit design complexity increases
Solution Approach 1:
The patent implements a universal common electrical node that serves multiple functions: it acts as the bottom plate connection during charge accumulation, provides the switched voltage connection during resolution, and serves as a common reference for all ADCs in the array. This multi-functional node reduces overall circuit complexity compared to having separate dedicated circuits for each function, while ensuring consistent ADC output through the common circuit ramp method.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves consistent ADC output across multiple units, reduces power consumption, and addresses the limitations of device mismatch and high voltage requirements, making it suitable for large-scale analog in-memory compute implementations.
Implementation Method 1
a capacitor configured to store the input charge and develop a voltage across the capacitor that is proportional to the input charge
Data Source
AI summary
The patent presents method of implementing a large number of ADC's in column pitch of array using a charge accumulation and measurement method on each bit line. The method uses a common voltage ramp node across ADC's with individual ADC floating node sensing so as to reduce power consumption while maintaining ADC accuracy. Systematic errors between program verify mode and MAC inference mode between accumulation and sense are eliminated inherently.