Time-Interleaved ADC Clock Delay Correction for Phase Mismatch
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) in high-data rate communication applications suffer from sample time mismatches among channel ADCs, leading to increased noise in the output due to timing errors, which are a primary limiting factor.
Innovation Solution
A method for phase mismatch correction in high-sample rate time-interleaved ADCs involves a phase-mismatch detector driving a control circuit for the clock generator, using a decimating low-pass filter to modify the clock path delay while keeping the signal path unaltered, with components including a common mode logic buffer, non-overlapping generator, and digital-to-analog converter (DAC), allowing adaptive correction without limiting input signal bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved ADC architecture is used to increase sampling rate, then productivity is improved, but sample time mismatch errors increase causing higher noise
Solution Approach 1:
The patent implements a feedback mechanism where the output of the time-interleaved ADC array is fed to a phase-mismatch detector that measures timing errors. The detector output is then used to adjust the clock signals via a control circuit, creating a closed-loop system that continuously corrects sample time mismatches and reduces output noise while maintaining high sampling rates
Solution Approach 2:
The patent dynamically changes the clock signal parameters (phase and timing) based on detected mismatch errors. The control circuit modifies clock signal characteristics in real-time to compensate for timing variations between parallel ADC channels, thereby reducing noise without sacrificing the high sampling rate capability
2Measurement precision
If digital filters are used to correct timing errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a phase-mismatch detector as an intermediary component that specifically measures timing errors between channels. This dedicated measurement mechanism provides precise error information that drives the correction process, achieving high measurement precision without requiring complex full-bandwidth digital filtering structures
3Measurement precision
If clock path delay is modified to correct phase mismatch, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic adjustment of clock path delays through a control circuit that responds to real-time mismatch detection. The delay elements in the clock generator are made adjustable rather than fixed, allowing the system to adaptively correct phase errors while using a relatively simple control architecture that monitors and adjusts only the necessary clock parameters
Data Source
AI summary
A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.