ADC Sampling Clock Circuit With Variable Resistance Delay Tuning
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Solution Overview
Problem
The existing sampling clock generating circuits for Analog to Digital Converters (ADCs) face limitations in adjusting timing offsets between sampling points, leading to non-uniform interlaced sampling and reduced conversion precision due to the inability to effectively adjust timing offsets caused by phase inverters with limited delay capabilities.
Innovation Solution
A sampling clock generating circuit incorporating a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where the variable resistance circuit changes resistance values at specific intervals, allowing for precise adjustment of timing offsets by maintaining the output signal at a high level for a controlled duration, enabling the cancellation of timing offsets between sampling points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase inverters are connected in series in transmission channels to delay signals, then sampling clocks at different phases are generated, but timing offset between sampling points cannot be effectively adjusted due to limited delay capability (only as low as 20 ps)
Solution Approach 1:
The patent changes the resistance values of resistors in the transmission channels to adjust the delay time of phase inverters. By varying resistance parameters, the timing offset between sampling points can be precisely controlled without increasing circuit complexity. Each phase inverter channel includes resistors with adjustable resistance values that directly affect the delay characteristic.
Solution Approach 2:
The patent introduces adjustable and可调 resistors that allow dynamic adjustment of delay time. The resistance values can be changed during operation to compensate for timing offsets, making the system adaptable rather than fixed. This dynamic adjustment capability enables precise timing offset correction.
2Productivity
If logic circuit divides clock source signal into n channels, then n channels of signals with different phases are obtained, but timing offset in picoseconds (ps) occurs between sampling points due to process and device development limitations
Solution Approach 1:
The patent adjusts resistance parameters in the transmission channels to compensate for timing offsets introduced by logic circuit division. By changing resistance values, the delay time of each channel can be tuned to ensure uniform sampling points across all n channels, maintaining sampling point uniformity while achieving high sampling frequency.
Solution Approach 2:
The patent implements a feedback mechanism where the timing offset between sampling points is measured and used to adjust the resistance values of resistors in the transmission channels. This closed-loop control ensures that sampling points remain uniform despite variations in logic circuit performance due to process limitations.
3Productivity
If multiple ADC chips perform interlaced sampling driven by sampling clocks at different phases, then higher sampling frequency is implemented, but conversion precision of ADC is reduced due to non-uniform sampling caused by timing offset
Solution Approach 1:
The patent adjusts resistance values in the transmission channels to eliminate timing offsets between sampling clocks driving multiple ADC chips. This ensures uniform sampling across all chips, maintaining high conversion precision while enabling higher sampling frequencies through interlaced sampling.
Solution Approach 2:
The patent introduces dynamically adjustable resistance elements that allow real-time compensation for timing offsets. This dynamic adjustment ensures that multiple ADC chips perform synchronized sampling, maintaining conversion precision while achieving higher overall sampling rates through the parallel interlaced sampling architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively adjusts timing offsets with high precision, reaching hundreds of femtoseconds, thereby improving the conversion precision of ADCs and avoiding harmonic distortion, and enhancing the Spurious Free Dynamic Range (SFDR).
Implementation Method 1
the output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded
Implementation Method 2
the variable resistance circuit is configured to change a resistance value at intervals of duration T
Implementation Method 3
the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level
Data Source
AI summary
A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.