ADC Clock Synchronization With Filter Reset for Low Phase Error
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Solution Overview
Problem
Multi-channel instruments face synchronization issues due to phase errors between ADC outputs, particularly in systems with geographically separated components, requiring complex hardware circuitry and increased phase errors without precise timing relationships.
Innovation Solution
A method involving stopping and restarting the master clock of ADC systems to synchronize sampling with a time reference, using a single master clock signal and internal filter reset to ensure precise timing synchronization without additional hardware or isolation components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex hardware circuitry with multiple input/output arrangements and multiple system clocks is used for ADC synchronization, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple synchronization functions into a single master clock signal that controls all ADC channels. Instead of using separate synchronization circuits for each ADC, a unified clock distribution system is implemented where the master clock simultaneously drives all ADC units, eliminating the need for multiple independent synchronization hardware paths.
Solution Approach 2:
The master clock signal serves multiple functions: it provides the sampling clock for all ADC channels, acts as the synchronization reference, and enables deterministic timing relationships across all channels. This multi-functional approach replaces what would traditionally require separate synchronization circuits, input/output arrangements, and multiple system clocks.
2Measurement precision
If multiple system clocks and complex hardware circuitry are used for ADC synchronization, then phase error reduction is improved, but manufacturing cost increases
Solution Approach 1:
The patent consolidates multiple clock sources into a single master clock, reducing the number of components that need to be manufactured and assembled. This merging approach eliminates the need for multiple system clocks and associated hardware circuitry, directly reducing manufacturing complexity and cost while maintaining phase synchronization accuracy.
Solution Approach 2:
Instead of using multiple independent clock sources, the system creates synchronized clock signals by distributing copies of the single master clock to all ADC channels. This copying approach ensures identical timing relationships across all channels without requiring multiple physical clock sources, reducing component count and manufacturing cost.
3Device complexity
If a single master clock signal is used for ADC synchronization, then device complexity is reduced, but synchronization precision may be compromised
Solution Approach 1:
The system performs preliminary synchronization by resetting the internal filters of all ADC channels to a known initial state before resuming operation. This preliminary action ensures that all channels start from the same reference point, maintaining synchronization precision even with a single master clock. The deterministic restart mechanism ensures that all ADCs begin sampling at precisely the same clock edge.
Solution Approach 2:
The system monitors the synchronization status and timing relationships between ADC channels, using feedback mechanisms to ensure that the single master clock maintains precise timing relationships. The feedback ensures that phase errors remain within acceptable limits despite the simplified clock architecture.
Data Source
AI summary
A method for synchronizing an analog-to-digital converter, ADC, the method comprising: stopping, by a processor, a master clock signal to the ADC to pause sampling of the ADC, the master clock signal being supplied by an external master clock to the ADC; detecting, by the ADC, that a synchronization event has occurred whilst the master clock is stopped; restarting, by the processor, the master clock signal to the ADC; resetting, by the ADC, an internal filter at a time that is synchronous with the master clock; and resuming, by the ADC, sampling in response to resetting the internal filter of the ADC.