Interleaved ADC Clock Generation With Synchronized Inverted Phases
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Solution Overview
Problem
Conventional clock signal generating devices for A/D converters with interleaved constitution suffer from timing differences between channels due to phase delays, degrading conversion precision by causing sampling point mismatches.
Innovation Solution
A clock signal generating device utilizing three Delayed Flip Flops to ensure two clock signals with 180° phase difference are outputted at the same timing, eliminating timing differences between channels by using feedback loops within the flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single Delayed Flip Flop is used to generate two inverted clock signals, then the device complexity is reduced, but timing differences occur between the clock signals due to phase delays
Solution Approach 1:
The patent divides the single flip-flop function into three separate Delayed Flip Flops (101, 102, 103), where each flip-flop handles a specific portion of the clock signal generation. This segmentation allows independent optimization of each flip-flop's timing characteristics, eliminating the timing differences that would occur in a single flip-flop design while maintaining manageable device complexity.
Solution Approach 2:
The patent implements feedback connections where the output of each Delayed Flip Flop is fed back to its own input (101: Q→D, NQ→D; 102: Q→D; 103: NQ→D). This feedback mechanism ensures that each flip-flop synchronizes its output transitions with the clock signal, maintaining precise timing relationships between the generated clock signals CLK_A and CLK_B.
2Productivity
If two clock signals with 180° phase difference are generated using conventional methods, then the A/D converter can process both channels in parallel, but sampling timing differences occur between channels
Solution Approach 1:
The patent performs preliminary timing adjustment by configuring three Delayed Flip Flops with specific feedback connections before the clock signals are used for sampling. The flip-flops are pre-synchronized to ensure that CLK_A and CLK_B have exactly 180° phase difference and identical timing characteristics, eliminating the need for subsequent timing corrections and ensuring precise simultaneous sampling across both A/D converter channels.
Solution Approach 2:
The patent uses asymmetric configurations of the three Delayed Flip Flops, where flip-flop 101 handles both Q and NQ outputs with feedback, flip-flop 102 handles only Q output, and flip-flop 103 handles only NQ output. This asymmetric arrangement allows precise control over the phase relationship between CLK_A and CLK_B, ensuring they are exactly 180° out of phase while maintaining identical timing characteristics for high-precision parallel sampling.
Data Source
AI summary
A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.