Image Sensor ADC Clock Masking for DNL and CFPN Reduction
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Solution Overview
Problem
Image sensors suffer from differential non-linearity (DNL) and column fixed pattern noise (CFPN) due to overlapping reset periods of pixel circuits, leading to non-uniform analog voltage ranges and repetitive digital signal errors.
Innovation Solution
An analog-to-digital converter (ADC) circuit that masks the system clock signal using an internal clock generator to generate synchronized clock signals, allowing for individual clock cycles for each pixel circuit, thereby reducing repetitive reset counts and improving digital signal uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ADC circuit uses a correlated double sampling method with uniform clock signaling, then the conversion process is simple and efficient, but differential non-linearity and column fixed pattern noise occur due to overlapping reset periods
Solution Approach 1:
The patent applies parameter changes by modifying the clock signal characteristics (masking specific clock cycles) to prevent overlapping reset periods. By changing the temporal parameters of the clock signal rather than the hardware structure, the system achieves both efficient conversion and uniform signal output without DNL or CFPN artifacts.
Solution Approach 2:
The patent introduces dynamic clock signal control where the clock generator dynamically masks specific clock cycles based on the sequential driving state of pixel circuits. This dynamic adjustment ensures that reset periods do not overlap across columns while maintaining the overall efficiency of the ADC conversion process.
2Device complexity
If the system uses a single system clock signal for all pixel circuits, then the clock distribution is simple and synchronized, but DNL artifacts repeat across columns due to identical counting patterns
Solution Approach 1:
The patent segments the single system clock signal into multiple column-specific clock signals by selectively masking clock cycles. Each column receives a differentiated clock signal pattern that prevents identical counting patterns across columns, thereby eliminating repeating DNL artifacts while maintaining manageable clock distribution through a systematic masking approach.
3Productivity
If the ADC circuit processes multiple pixel circuits simultaneously with overlapping reset periods, then the processing speed is high, but column fixed pattern noise is generated due to correlated DNL errors
Solution Approach 1:
The patent applies preliminary anti-action by proactively masking specific clock cycles before the ADC conversion process begins. This preventive measure ensures that reset periods for different columns do not overlap, thereby preventing the generation of CFPN and DNL artifacts before they can occur during simultaneous processing of multiple pixel circuits.
Data Source
AI summary
An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.