ADC Sampling Clock RC Timing Offset Correction
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Solution Overview
Problem
The existing sampling clock generating circuits for analog to digital converters (ADCs) face limitations in adjusting timing offsets between sampling points, leading to non-uniform interlaced sampling and reduced conversion precision due to the inability to effectively adjust timing offsets, resulting in harmonic distortion and decreased Spurious Free Dynamic Range (SFDR).
Innovation Solution
A sampling clock generating circuit utilizing an RC circuit formed by a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where the capacitor discharges slowly due to the RC circuit, allowing the output signal to maintain a high level for a period before transitioning to low, enabling precise adjustment of timing offsets between sampling points by varying the resistance value, thereby correcting timing offsets and improving ADC precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase inverters are connected in series in transmission channels to delay signals, then sampling clocks at different phases are generated, but the timing offset between sampling points cannot be effectively adjusted (only 20 ps delay available)
Solution Approach 1:
The patent changes the resistance parameter in the RC circuit to adjust the discharge time constant, thereby controlling the duration of the high level output signal. By varying the resistance value, the timing offset can be precisely adjusted to cancel the timing offset introduced by the logic circuit, achieving timing offset adjustment precision of hundreds of femtoseconds without increasing circuit complexity.
2Adaptability or versatility
If logic circuit divides clock source signal into n channels, then n channels of signals with different phases are obtained, but timing offset in picoseconds occurs between sampling points
Solution Approach 1:
The patent applies preliminary action by introducing an RC circuit at the output of the logic circuit to pre-adjust the timing of the divided clock signals. The RC circuit generates a delayed version of the clock signal that compensates for the timing offset introduced by the logic circuit division, ensuring that all n channels of sampling clocks have synchronized sampling points before being applied to the ADC chips.
3Productivity
If timing offset between sampling points cannot be adjusted, then interlaced sampling is non-uniform and harmonic occurs
Solution Approach 1:
The patent implements a feedback mechanism where the output signal of the logic circuit is fed back through the RC circuit, and the delayed signal is used to adjust the timing of the sampling clocks. This feedback loop continuously compensates for timing offsets, ensuring uniform interlaced sampling and eliminating harmonic distortion while maintaining high sampling frequency capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise adjustment of timing offsets with hundreds of femtosecond precision, preventing harmonic distortion and enhancing the Spurious Free Dynamic Range (SFDR) and overall conversion precision of the ADC.
Implementation Method 1
An RC circuit is formed by using a resistance variable circuit, a NOT-gate type circuit, and a capacitor, and when a pulse signal is changed from a low level to a high level, the capacitor discharges by using the RC circuit
Data Source
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AI summary
The present invention relates to the field of digital signal processing, and discloses a sampling clock generating circuit and an analog to digital converter. The sampling clock generating circuit includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level; and the resistance variable circuit is configured to change a resistance value at intervals of duration T, where the resistance value is changed based on a period of n*T, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer. The present invention improves conversion precision of the ADC.