ADC Clock Phase Selection for Low-Rate NB-IoT Reception
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Solution Overview
Problem
Existing LTE solutions are unsuitable for supporting millions of low-cost IoT devices due to either increased financial and power costs at higher sampling rates or performance degradation at cost-efficient rates, which negatively impacts uplink transmission timing in Narrow-Band IoT (NB-IoT) devices.
Innovation Solution
A receiver circuit with an analog-to-digital converter (ADC) and a clock divider circuit that adjusts the sampling rate and phase to align with OFDM symbol timing, allowing for reduced sampling rates while minimizing inter-symbol interference, using a successive approximation ADC and configurable phase selection to optimize power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher sampling rates are used to maintain signal quality, then measurement precision is improved, but use of energy and device cost increase
Solution Approach 1:
The patent applies dynamics by making the sampling rate adjustable rather than fixed. The receiver circuit dynamically adapts the sampling rate based on signal conditions and requirements, allowing optimization between power consumption and signal quality. The clock divider circuit enables flexible sampling rate selection to match actual needs.
Solution Approach 2:
The patent changes the sampling rate parameter from a fixed high value to a variable parameter that can be optimized. By adjusting the sampling rate according to specific signal requirements and using phase alignment techniques, the system achieves acceptable signal quality at lower sampling rates, thereby reducing power consumption.
2Use of energy by moving object
If lower sampling rates are used to reduce power consumption, then use of energy is improved, but measurement precision deteriorates
Solution Approach 1:
The patent applies preliminary action by performing phase alignment and timing adjustment before sampling occurs. The clock divider circuit pre-adjusts the sampling clock phase to align with the OFDM symbol timing, ensuring that even at lower sampling rates, the critical signal information is captured accurately. This preliminary timing adjustment compensates for the reduced sampling frequency.
Solution Approach 2:
The clock divider circuit acts as an intermediary between the reference clock and the ADC sampling clock. It introduces a controllable phase shift that mediates between the fixed reference clock frequency and the variable sampling requirements, enabling accurate sampling at lower rates by aligning the sampling instants with signal boundaries.
3Measurement precision
If adjustable phase selection is implemented to align sampling with OFDM symbols, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by separating the clock generation function into distinct stages: a reference clock source and a clock divider circuit with phase selection capability. This segmentation allows the phase adjustment function to be added modularly without redesigning the entire clock system, thereby managing complexity through functional decomposition.
Solution Approach 2:
The clock divider circuit serves multiple functions: frequency division, phase adjustment, and timing synchronization. By making this single circuit element multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby achieving improved sampling alignment without proportionally increasing overall device complexity.
Data Source
AI summary
Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.