ADC Clock Phase Selection for Low-Rate NB-IoT Receiver Timing
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Solution Overview
Problem
Existing LTE solutions are unsuitable for supporting millions of low-cost IoT devices due to either increased financial and power costs at higher sampling rates or performance degradation at cost-efficient rates, which negatively impacts uplink transmission timing in Narrow-Band IoT (NB-IoT) devices.
Innovation Solution
A receiver circuit with an analog-to-digital converter (ADC) and a clock divider circuit that adjusts the sampling rate and phase to align with OFDM symbol timing, allowing for reduced sampling rates while minimizing inter-symbol interference, using a successive approximation ADC and configurable phase selection to optimize power and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing LTE solutions are used for NB-IoT devices, then device functionality is achieved, but financial cost and power consumption increase
Solution Approach 1:
The patent changes the sampling rate parameter from conventional LTE rates to specifically optimized rates for NB-IoT (e.g., 30.72 MHz for downlink, 15.36 MHz for uplink). This parameter optimization allows the ADC to operate at lower, more energy-efficient rates while maintaining the required functionality for NB-IoT's narrower bandwidth (200 kHz effective bandwidth), thereby reducing power consumption without sacrificing device functionality.
2Use of energy by moving object
If sampling rate is reduced for cost efficiency, then power consumption decreases, but performance degradation occurs
Solution Approach 1:
The patent optimizes multiple parameters simultaneously: sampling rate (reduced to NB-IoT specific rates), bandwidth (configured for 200 kHz effective bandwidth), and subcarrier spacing (15 kHz). These coordinated parameter changes ensure that the reduced sampling rate still captures all necessary signal information for NB-IoT operation, maintaining performance while achieving lower power consumption.
Solution Approach 2:
The patent implements dynamic phase adjustment of the sampling clock to align with OFDM symbol timing. This dynamic adaptation ensures that even at reduced sampling rates, the sampling instances correctly capture OFDM symbols without inter-symbol interference, thereby maintaining signal integrity and performance despite the lower sampling rate.
3Ease of manufacture
If sampling rate is reduced, then device cost decreases, but uplink transmission timing accuracy deteriorates
Solution Approach 1:
The patent implements dynamic phase adjustment of the sampling clock to align precisely with OFDM symbol timing boundaries. This dynamic timing alignment ensures that even at reduced sampling rates, the sampling instances correctly capture the start and end of OFDM symbols, maintaining accurate uplink transmission timing without requiring higher sampling rates, thus enabling lower-cost device implementation.
4Adaptability or versatility
If conventional LTE receiver circuits are used, then compatibility is achieved, but power consumption and cost increase
Solution Approach 1:
The patent applies local quality optimization by configuring the ADC and clocking circuitry specifically for NB-IoT requirements rather than using general-purpose LTE receiver circuits. The ADC is configured with NB-IoT optimized sampling rates and the clock divider is configured with specific division ratios (e.g., 64, 128, 256) to generate precise sampling clocks for NB-IoT bandwidth (200 kHz effective), eliminating the need for higher sampling rates required by conventional LTE, thereby reducing power consumption while maintaining NB-IoT compatibility.
Data Source
AI summary
Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.