Clock Data Recovery Using ADC Samples for Low-Latency Phase Timing
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Solution Overview
Problem
Existing communication systems face challenges in adjusting timing skew of clocks due to environmental factors, leading to reduced reliability in signal communication, particularly when using multi-level signals, and methods like Mueller-Muller Phase Detection (MMPD) can introduce latency.
Innovation Solution
A receiving device evaluates clock timing using analog-to-digital converter outputs without relying on equalizer outputs, employing a delay buffer, phase interpolator, and clock data restorer to determine slope and curve types, thereby adjusting clock timing accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Mueller-Muller Phase Detection (MMPD) is used to detect clock phase, then clock timing can be adjusted, but loop latency increases
Solution Approach 1:
The patent extracts the clock phase detection function from the equalizer output path and implements it directly using ADC outputs. The phase detector receives digital samples directly from the ADC group, bypassing the equalizer processing chain, thereby reducing loop latency while maintaining detection accuracy
Solution Approach 2:
The patent introduces an intermediary processing stage where digital samples from the ADC are directly fed to the phase detector. This intermediary path eliminates the need for equalizer processing before phase detection, reducing the overall loop latency while preserving the ability to accurately detect clock phase
2Reliability
If equalizer output is used for clock timing adjustment, then timing skew can be corrected, but loop latency occurs
Solution Approach 1:
The patent extracts the timing adjustment function from the equalizer output path and implements it using direct ADC outputs. The phase detector and timing adjustment mechanism operate independently of the equalizer processing chain, eliminating the latency introduced by equalizer processing while maintaining timing skew correction capability
Solution Approach 2:
The patent performs preliminary phase detection and timing adjustment using direct ADC samples before the signal enters the equalizer processing chain. This preliminary action allows timing skew to be corrected early in the signal path, avoiding the need to process through the equalizer and thereby reducing overall loop latency
Data Source
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AI summary
A receiving device includes a delay buffer configured to receive an analog signal and output a delayed analog signal, a phase interpolator configured to output a clock signal based on a phase compensation code signal and a reference clock signal, an analog-to-digital converter group configured to output a slope type determination signal indicating a slope of the analog signal based on the analog signal and the delayed analog signal, and a clock data restorer. The clock data restorer is configured to determine a curve type associated with a plurality of digital samples from the analog-to-digital converter group. The clock data restorer also evaluates a timing of the clock signal based on the curve type and the slope type determination signal, and outputs the phase compensation code signal to move the sample timing closer to an optimum timing.