ADC Sampling Clock RC Delay for Timing Offset Correction
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Solution Overview
Problem
The existing sampling clock generating circuits for Analog to Digital Converters (ADCs) face challenges in adjusting timing offsets between sampling points, leading to non-uniform sampling and reduced conversion precision due to limitations in phase inverter delays, resulting in harmonic distortion and reduced spurious free dynamic range (SFDR).
Innovation Solution
A sampling clock generating circuit incorporating a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where the resistance variable circuit changes resistance values at specific intervals, allowing for precise adjustment of timing offsets by controlling the duration of high-level signals, thereby forming an RC discharge circuit that adjusts the timing offset between sampling points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase inverters are connected in series in transmission channels to delay signals, then sampling clocks at different phases are generated, but the timing offset between sampling points cannot be effectively adjusted due to limited delay capability (only as low as 20 ps)
Solution Approach 1:
The patent changes the resistance values in the RC delay circuit dynamically to adjust the delay time. By varying the resistance parameter, the timing offset between sampling points can be precisely controlled beyond the fixed 20 ps limitation of conventional phase inverters, achieving adjustable delay while maintaining circuit simplicity
Solution Approach 2:
The patent introduces dynamic control of the delay circuit by using controllable switches to adjust resistance values in real-time. This transforms the static delay of conventional phase inverters into a dynamic, adjustable delay mechanism, enabling precise timing offset correction without increasing device complexity
2Productivity
If logic circuits divide clock source signal into n channels, then n channels of signals with different phases are obtained, but timing offset in picoseconds occurs between sampling points due to process and device development limitations
Solution Approach 1:
The patent introduces an RC delay circuit as an intermediary element between the clock division and ADC sampling stages. This intermediary circuit provides the necessary timing correction to compensate for the picosecond-level offsets introduced by logic circuit divisions, ensuring uniform sampling points while maintaining high sampling frequency capability
Solution Approach 2:
The patent applies preliminary delay adjustment to the clock signals before they reach the ADC chips. By pre-correcting the timing offsets in the clock distribution network, the sampling points become uniform, preventing the harmonic distortion that would otherwise occur during interlaced sampling
3Productivity
If multiple ADC chips perform interlaced sampling with non-uniform sampling points, then higher sampling frequency is achieved, but conversion precision is reduced due to harmonic distortion
Solution Approach 1:
The patent applies preliminary correction to prevent the timing offset problem before it affects conversion precision. By pre-adjusting the clock phases to achieve uniform sampling points, the patent prevents the generation of harmonic distortion that would otherwise degrade ADC conversion precision, enabling high-frequency interlaced sampling to maintain accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively corrects timing offsets with high precision, reaching hundreds of femtoseconds, preventing harmonic distortion and enhancing ADC conversion precision and SFDR by maintaining high-level signals for controlled durations before transitioning to low levels.
Implementation Method 1
the other end of the capacitor is grounded... forming an RC discharge circuit that adjusts the timing offset between sampling points
Implementation Method 2
the resistance variable circuit comprising n gating switches, is configured to change a resistance value at intervals of duration T between n resistance values
Data Source
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AI summary
The present invention relates to the field of digital signal processing, and discloses a sampling clock generating circuit and an analog to digital converter. The sampling clock generating circuit includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high electrical level, output a low electrical level; and when the pulse signal is a low electrical level, output a high electrical level; and the resistance variable circuit is configured to change a resistance value at intervals of duration T, where the resistance value is changed based on a period of n*T, and resistance values after changes within each period are different from each other, where n≥2 and n is an integer. The present invention improves conversion precision of the ADC.