ADC Receiver Clock Recovery Using Multi-Phase Sampling
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Solution Overview
Problem
High-speed communication interfaces face challenges in reducing clock recovery latency, particularly at low baud rates, which leads to increased jitter and misidentification of data symbols, affecting the performance of ADC-based receiver circuits in interconnect standards like PCIe.
Innovation Solution
The implementation of multiple analog-to-digital converter (ADC) circuits that sample at corresponding times, combined with techniques such as decimation and serialization, to reduce clock recovery latency and improve jitter tolerance by adjusting the number of active ADCs based on baud rate and aligning samples with different clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single ADC circuit is used to sample the equalized signal, then the device complexity is reduced, but the clock recovery latency increases particularly at low baud rates
Solution Approach 1:
The patent divides the sampling function across multiple ADC circuits (first ADC, second ADC, etc.) that operate in parallel or sequence. Each ADC samples the equalized signal during different time periods, allowing the system to process multiple samples simultaneously or in rapid succession, thereby reducing the overall clock recovery latency without requiring a single complex high-speed ADC
Solution Approach 2:
The patent employs periodic sampling where different ADC circuits are activated during different time periods in a cyclic manner. The sample circuit selectively activates a first ADC during a first time period and a second ADC during a second time period, creating a periodic sampling pattern that reduces latency by ensuring samples are taken at optimal intervals while distributing the workload across multiple converters
2Loss of time
If the number of active ADC circuits is increased to reduce latency, then the clock recovery latency decreases, but the power consumption increases
Solution Approach 1:
The patent implements dynamic configuration where the number of active ADC circuits is adjusted based on operating conditions such as baud rate. The sample circuit selectively activates a subset of ADC circuits from the plurality available, allowing the system to use more ADCs when low latency is critical (high baud rates) and fewer ADCs when power consumption is more important (low baud rates), creating a dynamic trade-off optimization
Solution Approach 2:
The patent changes the operational parameters of the ADC circuitry by adjusting the number of actively sampling converters based on the baud rate of the serial data stream. At higher baud rates where latency is more critical, more ADC circuits are activated; at lower baud rates, fewer ADC circuits remain active, thereby adapting the power consumption and latency characteristics to match the actual communication requirements
3Loss of time
If sampling is performed at high frequency to reduce latency, then the clock recovery latency decreases, but the jitter tolerance decreases leading to misidentification of data symbols
Solution Approach 1:
The patent performs preliminary equalization of the signal before sampling by using a front-end circuit to generate an equalized signal from multiple signals that encode the serial data stream. This pre-processing compensates for channel distortions and prepares the signal for optimal sampling, allowing the system to use lower sampling frequencies that are more tolerant to jitter while still achieving low latency through the coordinated operation of multiple ADC circuits
Solution Approach 2:
The patent employs a recovery circuit that generates a recovered clock signal and recovered data symbols from the samples, which can be used to provide feedback for optimizing the sampling timing and clock recovery. This feedback mechanism allows the system to adapt to jitter conditions by adjusting the sampling phases and timings based on the actual recovered data quality, thereby maintaining reliability even when operating at reduced sampling frequencies
Data Source
AI summary
A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.