SAR-Flash ADC Clock-State Partitioning for Multi-Bit Conversion
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Solution Overview
Problem
Successive approximation register analog-to-digital converters (SAR ADCs) are limited by only obtaining one bit per clock cycle, making fast operation difficult, while flash ADCs require an exponentially increasing number of comparators and DACs as the number of digital bits increases, leading to increased cost and size.
Innovation Solution
Combining SAR ADC with a flash ADC, where the SAR ADC determines one bit during a first clock state and the flash ADC determines additional bits during a second state, using a clock generator, DAC, comparator, and SAR/flash logic units to generate analog signals and determine digital bits, with a capacitor configuration to enhance comparator operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SAR ADC is used to obtain digital bits by successively comparing analog input signal per clock cycle, then the circuit complexity is reduced, but the conversion speed decreases because only one bit can be obtained per clock cycle
Solution Approach 1:
The conversion process is segmented into two distinct phases within one clock cycle: a first state for obtaining the most significant bit using SAR ADC, and a second state for obtaining the remaining less significant bits using flash ADC. This segmentation allows each converter type to operate in its optimal mode, combining the low complexity of SAR ADC with the high speed of flash ADC.
Solution Approach 2:
The system dynamically switches between SAR ADC and flash ADC operations based on the clock signal state. The converter type is not fixed but adapts during the conversion process, enabling the system to achieve both low complexity and high speed by utilizing the strengths of each converter type at appropriate moments.
2Speed
If flash ADC is used to obtain multiple digital bits by comparing analog input signal with various reference levels at one time, then the conversion speed increases, but the number of comparators and DACs increases exponentially
Solution Approach 1:
The bit conversion process is segmented such that only the less significant bits require multiple comparators in flash ADC mode, while the most significant bit uses the simpler SAR ADC approach. This reduces the overall number of comparators needed compared to a full flash ADC, as the exponential growth in comparator count is avoided for the most significant bit.
Solution Approach 2:
Different conversion strategies are applied to different parts of the digital output: the most significant bit uses SAR ADC with minimal comparators, while the less significant bits use flash ADC with multiple comparators. This local differentiation optimizes the overall system by applying complexity only where necessary for achieving high-speed conversion.
3Productivity
If the number of digital bits to be obtained in one step is increased in flash ADC, then the conversion speed increases, but the cost and size increase due to exponentially increased number of comparators and resistors
Solution Approach 1:
The digital bits are segmented into two groups: one bit obtained during the first state using SAR ADC, and three bits obtained during the second state using flash ADC. This segmentation enables the system to achieve high productivity (4 bits per clock cycle) while controlling device complexity, as the flash ADC only needs to handle 3 bits rather than all 4 bits simultaneously.
Data Source
AI summary
An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.