Time-Interleaved ADC Clocking With Transmission Gates for Low Skew
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Solution Overview
Problem
Conventional high-precision Analog-Digital Converters (ADCs) face challenges in achieving low time skew between clock signals, which affects conversion precision, especially in high-speed and high-frequency applications, as existing solutions using logic gates cannot meet the required linearity.
Innovation Solution
A clock generator using M transmission gates, such as CMOS, PMOS, or NMOS gates, performs gating control on a single clock signal to generate M second clock signals, where the phases form an arithmetic progression, reducing time skew by minimizing the impact of threshold voltage mismatching between MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional logic gates (D triggers) are used to generate multiple clock signals, then the clock signals can be generated through series connection, but the time skew between clock signals reaches picosecond level due to process deviation, which affects conversion precision
Solution Approach 1:
The patent replaces conventional logic gate-based clock signal generation (D triggers, AND gates) with a transmission gate-based system. This substitution eliminates the cumulative delay effects of series-connected logic gates, reducing time skew from picosecond to sub-picosecond level while maintaining the ability to generate multiple clock signals for time-interleaved ADC channels
Solution Approach 2:
The patent changes the fundamental parameter of clock signal generation from logic gate switching to transmission gate switching. By controlling the switching timing and duration of transmission gates, the system achieves precise clock signal distribution with minimal time skew, directly addressing the precision requirement of high-speed ADC conversion
2Productivity
If multiple D triggers are connected in series to generate clock signals, then clock signals can be distributed to multiple channels, but process deviation causes time skew at picosecond level, which introduces harmonic distortion
Solution Approach 1:
The patent substitutes the series-connected D trigger system with a parallel transmission gate system. Each channel receives its clock signal through a dedicated transmission gate controlled by a common clock source, eliminating the series accumulation of process deviations and preventing harmonic distortion while maintaining multi-channel distribution capability
Solution Approach 2:
The patent segments the clock distribution into independent parallel paths using separate transmission gates for each ADC channel. This segmentation isolates the clock signal paths, preventing inter-channel interference and time skew accumulation, thereby eliminating the harmful harmonics generated by series-connected logic gates
3Measurement precision
If retiming is performed using AND gates with same-source clock signal, then time skew can be reduced to hundreds of femtoseconds, but this cannot meet linearity requirement for high-frequency input signals in high-speed ADC
Solution Approach 1:
The patent replaces the retiming-based approach (using AND gates) with a direct transmission gate switching mechanism. This substitution provides more precise control over clock signal edges, achieving sub-picosecond time skew reduction that meets the stringent linearity requirements for high-frequency input signals in high-speed time-interleaved ADC systems
Data Source
AI summary
An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.