Time-Interleaved ADC Clocking With Feedback Non-Overlap Control
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Solution Overview
Problem
Time-interleaved analog to digital converters face challenges in maintaining low jitter for first-level clock signals and non-overlap conditions for second-level clock signals, especially as higher interleaving factors and speeds reduce timing margins, leading to degradation in ADC noise performance.
Innovation Solution
A clock generator that dynamically controls second-level clock signals using timing feedback to avoid overlap with first-level clock signals, employing adjustable delays and closed-loop feedback to maintain non-overlap conditions and reduce clock jitter, thereby improving ADC signal-to-noise distortion ratio (SNDR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher interleaving factors and speeds are used in time-interleaved ADC, then productivity is improved, but clock jitter increases and timing margins are reduced
Solution Approach 1:
The clock generation is divided into multiple hierarchical levels (first-level clocks for track-and-hold circuits, second-level clocks for sub-ADCs, and third-level clocks for individual channels). This segmentation allows each level to be optimized independently, enabling high-speed operation while maintaining low jitter through separate control mechanisms for each clock domain.
Solution Approach 2:
A feedback mechanism is implemented where the actual timing of first-level clock edges is detected and used to dynamically adjust the timing of second-level clock signals. This closed-loop feedback compensates for timing variations and maintains non-overlap conditions even at higher speeds, preventing jitter accumulation.
2Productivity
If higher interleaving factors are used, then productivity is improved, but timing margins are reduced leading to overlap conditions
Solution Approach 1:
The clock timing is made dynamic rather than fixed. Second-level clock signals are dynamically adjusted based on the actual arrival time of first-level clock edges detected through feedback. This dynamic adaptation allows the system to maintain adequate timing margins even with high interleaving factors, preventing overlap conditions that would occur with static timing.
3Reliability
If dynamic control with feedback is implemented, then clock jitter is reduced, but device complexity increases
Solution Approach 1:
The feedback control is segmented and distributed across multiple clock domains rather than implemented as a single complex centralized controller. Each clock level has its own simplified control logic that operates independently, reducing the complexity burden while achieving cumulative jitter reduction effects.
4Measurement precision
If non-overlap conditions are maintained for second-level clocks, then ADC SNDR is improved, but device complexity increases
Solution Approach 1:
The clock control system uses self-service mechanisms where the detection of first-level clock edges automatically triggers the adjustment of second-level clock timing. The system serves itself by using its own output signals as reference for control, eliminating the need for external complex control circuits while maintaining non-overlap conditions for improved SNDR.
Data Source
AI summary
A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.