ADC Low-Latency Coarse Output for Fast AGC Overrange Control

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Solution Overview

Problem

Analog-to-digital converters with more than one clock cycle latency can lead to overranging issues due to delayed gain adjustments in automatic gain control loops, particularly in systems with high sample rates and deterministic input signals, where fast transients may cause signal overrange before the AGC controller can react.

Innovation Solution

An improved analog-to-digital converter system provides a secondary, less than full precision and less than full latency coarse signal level indicator that can drive a fast attack circuit to quickly adjust the variable gain amplifier and prevent overranging, featuring a multi-bit or single-bit output derived from early stages of the converter, which can be used in pipeline, successive approximation, or ΔΣ systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the ADC output is used to implement a fast attack loop for AGC control, then the AGC controller can detect signal levels, but several samples could be overranged before the AGC controller has time to adjust the gain due to ADC latency

Engineering Contradiction:
Improvesignal level detection accuracyVSAvoidresponse time to overrange event
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts a coarse signal level indicator from an intermediate stage of the ADC conversion process, before the full conversion latency is complete. This preliminary indication allows the AGC controller to initiate gain adjustment actions earlier, before overrange events occur on subsequent samples.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the ADC conversion process into multiple stages, extracting a coarse signal level indicator from an intermediate stage rather than waiting for the final conversion result. This segmentation allows early detection of signal levels to drive the fast attack loop while the full precision conversion continues.

Inventive Principle:
Principle #1Segmentation

2Speed

If the ADC is run at a higher sample rate to shorten absolute response time to overrange events, then response speed improves, but the latency in clock cycles remains and overranging can still occur

Engineering Contradiction:
Improveabsolute response timeVSAvoidconversion latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

By extracting the coarse signal level indicator from an intermediate conversion stage, the system performs preliminary detection of signal levels that would eventually be fully converted. This allows the AGC controller to react before the full conversion completes, effectively reducing the functional latency impact.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If a full precision, full latency output is provided by the ADC, then measurement accuracy is maximized, but the output cannot be used for fast response control loops

Engineering Contradiction:
Improveoutput precisionVSAvoidcontrol loop response speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the ADC output into two separate outputs: a full precision full latency output for accurate measurement, and a coarse signal level indicator from an intermediate stage for fast control loop response. This segmentation allows both high precision measurement and fast control response to coexist.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ADC system provides multiple outputs serving different functions: the full precision output for measurement applications and the coarse indicator for control applications. This multi-functionality allows the same converter to support both accurate measurement and fast control without compromise.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7471229B2Analog-to-digital converter with low latency output path
Publication Date: 2008.12.30 ANALOG DEVICES INC
  • US7471229B2 patent drawing
  • US7471229B2 patent drawing
  • US7471229B2 patent drawing

AI summary

An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.