ADC Digital Error Correction Using Parallel Codeword Decoding
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Solution Overview
Problem
Conventional analog-to-digital converter (ADC) circuits face challenges in achieving high accuracy while balancing circuit complexity, sample rate, and cost, with existing error correction methods either increasing complexity or impacting conversion speed.
Innovation Solution
The proposed solution involves a dual-stage ADC architecture where two synchronously clocked ADC stages generate an n-bit code word with k bits as information and n-k bits as parity, decoded using error correction code to correct errors, allowing for improved accuracy without significant computational load or impact on analog precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional error correction methods are applied in ADC circuits, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The ADC is divided into multiple parallel sub-ADCs (first ADC, second ADC, third ADC, fourth ADC) that simultaneously convert different segments of the analog input signal. Each sub-ADC processes a portion of the signal range, and their digital outputs are combined through correction logic to achieve high-precision conversion. This segmentation allows error correction to be distributed across multiple simpler units rather than requiring a single complex error correction system.
Solution Approach 2:
The system performs preliminary analog-to-digital conversion in parallel through multiple sub-ADCs before final error correction. Each sub-ADC pre-processes a segment of the input signal independently, generating preliminary digital codes that are then combined and corrected. This preliminary parallel conversion approach enables error correction to be applied more efficiently to already-digital signals rather than requiring complex analog error correction.
2Measurement precision
If higher resolution ADCs are used to improve precision, then measurement precision is improved, but use of energy increases
Solution Approach 1:
Instead of using a single high-resolution ADC that would consume significant power, the system segments the conversion task across multiple lower-resolution sub-ADCs. Each sub-ADC operates at reduced resolution for its specific signal segment, and the combined output achieves the equivalent of high-resolution conversion. This segmentation distributes power consumption across multiple lower-power units, reducing total energy usage while maintaining precision.
Solution Approach 2:
The system uses multiple copies of simpler ADC circuits (four parallel sub-ADCs) rather than a single complex high-resolution ADC. Each copy performs a simplified conversion task, and their results are combined to achieve the precision of a single high-resolution converter. This copying approach allows the system to achieve high precision through parallel simpler units that collectively consume less power than a single high-resolution unit would require.
3Measurement precision
If more pipeline stages are added to improve accuracy, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The conversion process is segmented into parallel paths with multiple sub-ADCs operating simultaneously on different signal segments. This parallel segmentation enables high-precision conversion to occur in essentially the same time as simpler conversions, because multiple precision tasks are performed concurrently rather than sequentially. The sample rate is maintained high because the parallel architecture eliminates the need for sequential processing through multiple pipeline stages.
Solution Approach 2:
Instead of improving precision by adding sequential pipeline stages (time dimension), the system transitions to a parallel spatial architecture with multiple sub-ADCs operating simultaneously. This dimensional shift from sequential to parallel processing allows high precision to be achieved without increasing conversion time, thereby maintaining high sample rates while improving accuracy through spatial distribution of conversion tasks.
Data Source
AI summary
An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.