A/D Conversion Circuit With Common-Bias Ramp and Delay Synchronization
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Solution Overview
Problem
Existing analog-to-digital (A/D) conversion circuits in image-capturing devices face challenges in achieving uniform conversion results and managing chip area efficiently, particularly when noise affects the bias voltage, leading to uneven A/D conversion outcomes.
Innovation Solution
The proposed A/D conversion circuit incorporates a reference signal generation section with an integrator circuit and a clock generation section using delay units and constant current sources, synchronized by a common bias voltage, to generate a ramp wave and delay signals, respectively, facilitating precise comparison and counting for accurate digital data conversion without requiring additional synchronization circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a tdcSS-type ADC circuit is used for A/D conversion, then high S/N ratio can be achieved, but noise in the bias voltage causes uneven conversion results
Solution Approach 1:
The patent merges the bias voltage supply for the delay section and the ramp wave generation into a single common bias voltage source. This ensures that both sections experience the same noise conditions, making the noise effects common-mode and canceling each other out in the time measurement, thereby eliminating uneven conversion results while maintaining high S/N ratio
Solution Approach 2:
The patent introduces an intentional asymmetry in the circuit design by making the delay section and ramp wave generation section share a common bias voltage source, which is asymmetric compared to the conventional independent bias supplies. This asymmetric configuration ensures that noise affects both sections equally, transforming the problem into a common-mode noise scenario that can be differential-measured away
2Reliability
If synchronization circuits like phase-locked loops are added to synchronize the ramp wave and delay section, then uniform A/D conversion results can be achieved, but chip area increases
Solution Approach 1:
The patent extracts and removes the synchronization circuit (phase-locked loop) from the system by finding an alternative approach. Instead of using complex synchronization circuits, the invention uses a common bias voltage source to naturally synchronize the delay section and ramp wave generation, thereby achieving uniform conversion results without adding chip area
Solution Approach 2:
The common bias voltage source serves multiple functions simultaneously: it powers the delay section, generates the ramp wave, and acts as a synchronization mechanism. This multi-functionality eliminates the need for separate synchronization circuits, reducing chip area while maintaining conversion uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables synchronized operation of the ramp wave and delay section, suppressing noise-induced unevenness in A/D conversion results and reducing chip area requirements by eliminating the need for synchronization circuits like phase-locked loops.
Implementation Method 1
a reference signal generation section which has an integrator circuit having at least a capacitor and a first constant current source, and generates a reference signal changed in accordance with a constant current output by the first constant current source
Implementation Method 2
a clock generation section which has a delay section having a plurality of delay units delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source
Data Source
AI summary
An A/D conversion circuit includes: a reference signal generation section that includes an integrator circuit having a first constant current source and generates a reference signal that changes in accordance with a constant current output by the first constant current source; a comparison section that executes a comparison process between an analog signal and the reference signal and terminates the comparison process; a clock generation section that includes a delay section having delay units for delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source, and outputs a lower phase signal based on the signals output from the delay units; a latch section that latches the lower phase signal at a timing related to the termination of the comparison process; and a count section that counts a clock based on the lower phase signal.