ADC Common-Mode Calibration for Preamplifier Gain Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Analog-to-digital converters (ADCs) experience decreased preamplifier gain due to common mode voltage offsets caused by charge injection in track and hold circuits, leading to unbalanced operation points and reduced performance.
Innovation Solution
A conversion circuit with a feedback controller and common mode voltage circuit that selectively adjusts the common mode voltage to minimize offsets between input and reference voltages during the hold mode of the track and hold circuit, improving preamplifier gain through calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge injection in track and hold circuit is present, then the ADC input voltage increases during hold mode, but the common mode voltage offset increases causing preamplifier gain to decrease
Solution Approach 1:
The patent implements a feedback controller that monitors the common mode voltage offset and dynamically adjusts the common mode voltage of the reference signal to minimize the offset. The controller receives feedback about the offset magnitude and modifies the reference common mode voltage accordingly, creating a closed-loop system that continuously compensates for charge injection effects and maintains optimal preamplifier gain.
Solution Approach 2:
The patent changes the common mode voltage parameter of the reference signal dynamically during hold mode to compensate for charge injection. By adjusting this voltage parameter in response to detected offset conditions, the system maintains balanced operation points and prevents gain degradation despite the presence of charge injection in the track and hold circuit.
2Reliability
If common mode voltage offset increases, then the differential amplifier operates at un-balanced point, but the preamplifier gain decreases
Solution Approach 1:
The feedback controller continuously monitors the common mode voltage offset and adjusts the reference common mode voltage to maintain balanced operation points. This closed-loop control ensures that the differential amplifier operates at its optimal quiescent point despite variations in input common mode voltage or charge injection effects, thereby maintaining stable preamplifier gain.
Solution Approach 2:
The patent applies equipotentiality by adjusting the common mode voltage of the reference signal to match the common mode voltage of the input signal. By equalizing the common mode potentials at the differential amplifier inputs, the system eliminates unbalanced operation points and maintains optimal gain performance.
3Reliability
If calibration circuit is added to minimize common mode voltage offset, then preamplifier gain is improved, but device complexity increases
Solution Approach 1:
The feedback controller serves multiple functions: it monitors the common mode voltage offset, determines the appropriate compensation amount, and adjusts the reference common mode voltage. By consolidating these functions into a single multi-functional block, the patent reduces overall circuit complexity compared to implementing separate dedicated circuits for each function.
Solution Approach 2:
The patent introduces a common mode voltage adjustment circuit as an intermediary element that mediates between the reference signal source and the differential amplifier. This intermediary component provides a controlled interface for adjusting the reference common mode voltage without requiring direct modification of the main signal path, thereby simplifying the overall circuit architecture.
Data Source
AI summary
A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.