ADC Common-Mode Calibration for Preamplifier Gain Stability

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Solution Overview

Problem

Analog-to-digital converters (ADCs) face a decrease in preamplifier gain due to common mode voltage offsets caused by charge injection in track and hold circuits, leading to unbalanced operation points and reduced performance.

Innovation Solution

A calibration method and apparatus that utilize a conversion circuit with a feedback controller and common mode voltage circuit to minimize the common mode voltage offset between input and reference voltages during the hold mode of the track and hold circuit, improving the ADC preamplifier gain by adjusting the calibration voltage and common mode voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If charge injection in track and hold circuit is present, then the ADC input voltage changes during hold mode, but the common mode voltage offset increases causing preamplifier gain to decrease

Engineering Contradiction:
ImproveADC conversion accuracyVSAvoidpreamplifier gain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent applies preliminary action by performing calibration of the common mode voltage offset before actual ADC conversion operations. The calibration circuit pre-adjusts the offset caused by charge injection, ensuring that when the track and hold circuit enters hold mode, the preamplifier operates at the correct common mode voltage level, preventing gain degradation before it occurs

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through a calibration controller that monitors the common mode voltage offset and adjusts the calibration voltage accordingly. The system measures the offset caused by charge injection and feeds this information back to the calibration circuit, which then modifies the common mode voltage to compensate for the offset, creating a closed-loop control system that maintains optimal preamplifier gain

Inventive Principle:
Principle #23Feedback

2Measurement precision

If common mode voltage offset increases, then the differential amplifier operates at un-balanced point, but the preamplifier gain decreases

Engineering Contradiction:
Improvevoltage measurement accuracyVSAvoidpreamplifier gain
Core Design Contradiction:
Measurement precisionVSPower

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the common mode voltage parameter of the preamplifier. The calibration circuit modifies the common mode voltage level to compensate for offsets caused by charge injection, ensuring the differential amplifier operates at its optimal balanced point. This parameter adjustment restores the preamplifier gain without requiring changes to the amplifier's physical structure or operating principles

Inventive Principle:
Principle #35Parameter changes

3Reliability

If ADC input preamplifier gain decreases, then conversion performance is reduced, but additional calibration circuits increase device complexity

Engineering Contradiction:
ImproveADC conversion performanceVSAvoidcalibration circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the calibration function with the existing ADC structure by integrating the calibration circuit into the signal path of the track and hold circuit. The calibration voltage is injected through the same signal path used for normal operation, and the calibration controller utilizes the existing feedback path from the ADC output. This merging approach adds calibration capability without requiring completely separate independent circuits, thereby reducing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7466249B2System and method for common mode calibration in an analog to digital converter
Publication Date: 2008.12.16 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US7466249B2 patent drawing
  • US7466249B2 patent drawing
  • US7466249B2 patent drawing

AI summary

A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.