ADC Comparator Delay Compensation for Faster Sampling
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Solution Overview
Problem
Hybrid ADC architectures face a trade-off between comparator speed and linearity, leading to large delay that degrades sampling frequency and resolution, particularly in TDC-based converters.
Innovation Solution
A comparator circuit is used to detect the crossing point of an input analog signal and measure propagation delay, shifting the signal in the voltage domain to reduce delay, thereby improving sampling rate and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If comparator bandwidth is increased to reduce delay, then sampling frequency is improved, but linearity deteriorates
Solution Approach 1:
The ADC is divided into two stages: a first conversion stage (SAR ADC) that handles coarse conversion with high linearity, and a second conversion stage (TDC-based) that handles fine conversion with the comparator. This segmentation allows each stage to be optimized for its specific function, with the comparator only needing to resolve small residue voltages rather than the full input range, thus maintaining both speed and linearity.
Solution Approach 2:
The comparator is designed with specific local characteristics optimized for its function in the second stage: high bandwidth and low delay for fast switching between reference voltages, while the first stage SAR ADC maintains high linearity for the initial conversion. Each component has locally optimized properties suited to its specific role in the overall conversion process.
2Speed
If comparator delay is reduced to improve sampling rate, then power consumption increases
Solution Approach 1:
The comparator operates dynamically by rapidly switching between two reference voltages (+Vref and -Vref) rather than comparing against a single reference. This dynamic switching approach allows the comparator to achieve fast response times with reduced power consumption, as the high-speed switching is performed through controlled reference voltage transitions rather than continuous high-power operation.
Solution Approach 2:
The comparator's reference voltage parameter is changed dynamically between +Vref and -Vref levels. By modulating the reference voltage parameter in a controlled manner, the system achieves fast conversion without requiring the comparator to operate continuously at maximum power levels, thus reducing overall power consumption while maintaining high sampling rates.
Data Source
AI summary
Methods and systems for reducing delay in a comparator of an ADC are disclosed. In one embodiment, an ADC comprise a first analog-to-digital convertor stage. The ADC further comprises a second analog-to-digital convertor stage configured to receive the residue signal, output, a second digital value, and shift the residue signal by an amount based on a delay between the output of a digital value and a time of the first analog signal crossing an input reference signal. The ADC further comprises a combiner configured to receive the first digital value and the second digital value and combine the first digital value and the second digital value into an output representing a digital version of the first analog signal.