Comparator Averaging Layout for ADC Linearity Under Parasitic Resistance
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Solution Overview
Problem
Analog-to-digital conversion circuits face linearity degradation due to offset errors and parasitic resistance components generated during manufacturing, particularly when using resistors and metal routing, which affect the Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) especially when processing high-speed data.
Innovation Solution
The proposed solution involves an analog-to-digital conversion circuit with a comparator array and an averaging circuit that compensates for offset errors through optimized metal routing lengths and resistor configurations, where the metal routing lengths between comparators with minimum and maximum reference voltages are reduced, and resistors are used to minimize parasitic resistance variations, thereby improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal routing is used to connect comparators in parallel, then the circuit can be manufactured with standard processes, but parasitic resistance components are generated that degrade linearity
Solution Approach 1:
The patent applies asymmetry by making the metal routing lengths unequal: the first metal routing connecting comparators at opposite ends has a shorter length than the second metal routing connecting adjacent comparators. This asymmetric design compensates for parasitic resistance effects by deliberately creating unequal resistance values that cancel out offset errors in the averaging circuit, thereby improving linearity while maintaining standard manufacturing processes
Solution Approach 2:
The patent changes the parameter of metal routing length to optimize performance. By specifically designing the first metal routing to be shorter than the second metal routing, the parasitic resistance values are adjusted to achieve offset cancellation. This parameter change transforms the parasitic resistance from a harmful factor into a compensating element that improves linearity
2Reliability
If offset averaging technique with equal metal routing lengths is used, then offset errors are compensated, but parasitic resistance variations degrade linearity
Solution Approach 1:
The patent breaks the symmetry of equal metal routing lengths by making the first metal routing shorter than the second. This asymmetric configuration creates deliberate parasitic resistance differences that compensate for offset errors while the specific length ratios ensure that parasitic resistance variations do not degrade linearity,反而 improve it by canceling offset effects
3Adaptability or versatility
If longer metal routing is used between all comparators, then routing flexibility is improved, but parasitic resistance increases and degrades SNDR and SFDR
Solution Approach 1:
The patent applies local quality by differentiating the metal routing lengths for different comparator connections. The first metal routing between end comparators is made shorter to minimize parasitic resistance impact on critical paths, while the second metal routing between adjacent comparators can be longer. This localized optimization maintains routing flexibility while protecting signal quality in sensitive areas
Data Source
AI summary
An analog-to-digital conversion circuit includes a plurality of comparators and an averaging circuit. The averaging circuit is configured so that a length of a metal routing connected between output terminals of two comparators arranged on a leftmost side from among the plurality of comparators or a length of a metal routing connected between output terminals of two comparators arranged on a rightmost side from among the plurality of comparators is less than a length of a metal routing connected between output terminals of two comparators to which reference voltages having levels that are closest in magnitude are input.