SAR ADC Comparator Timing Correction for Metastability Errors
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Solution Overview
Problem
In successive approximation analog-to-digital converters (ADCs), metastability errors occur due to the uncertainty in the time the comparator takes to make a decision when differential inputs are close, leading to noise in the reference voltage shared among parallel ADCs, resulting in erroneous outputs.
Innovation Solution
A metastability detection and correction circuit is integrated into the ADC system, which monitors the comparator's output for metastable events and generates a correction code to ensure accurate bit value determination, even when the comparator fails to latch a decision within the allotted time, thereby preventing conversion errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the comparator decision time is extended to handle small differential inputs, then conversion accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The comparator is given a predetermined time interval to make a decision before the conversion cycle proceeds. This preliminary action ensures that even small differential inputs have sufficient time to be resolved, improving conversion accuracy without requiring indefinite delay of the processing cycle.
Solution Approach 2:
A metastability detection and correction circuit is introduced as an intermediary between the comparator and the conversion output. This circuit detects metastable events and generates correction codes, allowing the system to maintain high processing speed while correcting accuracy issues caused by metastability without extending the comparator decision time.
2Device complexity
If multiple ADCs share a common reference voltage, then device complexity is reduced, but reliability deteriorates due to noise coupling
Solution Approach 1:
The metastability detection and correction circuit monitors the comparator output and provides feedback when metastable events are detected. This feedback mechanism identifies conversion errors caused by noise coupling in shared reference voltages and generates correction codes, maintaining reliable conversions despite the presence of multiple ADCs sharing common references.
3Measurement precision
If the conversion time period is extended to ensure proper latching, then conversion accuracy is improved, but productivity deteriorates
Solution Approach 1:
The comparator is allocated a predetermined time interval within the conversion cycle to complete its decision and latch the bit value. This preliminary action ensures proper latching occurs before the conversion cycle proceeds, guaranteeing bit value determination accuracy without extending the overall conversion time period beyond standard timing.
Solution Approach 2:
The metastability detection and correction circuit acts as an intermediary that monitors whether proper latching occurred within the allotted time. When metastability is detected indicating improper latching, the circuit generates correction codes to fix the error, ensuring accurate bit determination without requiring extended conversion time periods.
Data Source
AI summary
A system and method are provided for the detection and correction of metastability errors in a successive approximation analog to digital converter (ADC). The successive approximation ADC (40) includes a comparator unit (424) that includes a NAND gate circuit (550) that outputs a comp_rdy_n signal when the comparator (500) has latched a result. ADC (40) includes a metastability detection and correction circuit (425) that includes a first logic circuit (700) that monitors the comp_rdy_n signal and detects a metastable event if that signal is not received within a portion of a conversion time period of the ADC. Responsive to detection of a metastable event, a second logic circuit (750) generates a correct conversion code at the output of the ADC. If no metastable event is detected during a conversion cycle of the ADC, the second logic circuit (750) outputs the conversion codes determined by the comparator (500).