Two-Stage ADC Comparator Architecture for Lower Power Conversion
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Solution Overview
Problem
The high power consumption of flash-type analog-to-digital converters due to the need for many voltage comparators operating in parallel for accurate AD conversion.
Innovation Solution
An analog-to-digital converter configuration that uses 2K+2 voltage comparators and 2L time comparators to compare an analog input voltage with reference voltages, generating a thermometer code and full binary codes to reduce the number of comparators needed for conversion, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If many voltage comparators are operated in parallel to achieve high accuracy AD conversion, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent divides the voltage comparison task into two stages: first, 2K+2 voltage comparators perform coarse comparison to identify the approximate voltage range; second, only 2L time comparators perform fine comparison within the identified range. This segmentation allows accurate AD conversion while significantly reducing the number of comparators operating simultaneously, thus lowering power consumption.
Solution Approach 2:
The voltage comparators perform preliminary comparison to determine which approximate voltage range the input voltage falls into before the time comparators perform the final precise comparison. This preliminary action eliminates the need for all comparators to operate simultaneously, as only the time comparators corresponding to the identified range need to operate in the second stage.
2Productivity
If 2N-1 voltage comparators are used for high speed parallel conversion, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the comparator system into two functional groups: voltage comparators for range identification and time comparators for precise measurement. This segmentation reduces the total number of comparators from 2N-1 to 2K+2 voltage comparators plus 2L time comparators, simplifying the device while maintaining high conversion speed through the parallel operation of the voltage comparators in the first stage.
Solution Approach 2:
The voltage comparators perform preliminary range identification in parallel to determine the active voltage range, which then enables the subsequent time comparators to focus only on the relevant range. This preliminary action maintains high conversion speed by using parallel processing where needed while reducing overall device complexity by eliminating redundant comparators.
Data Source
AI summary
An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.