SAR ADC Comparator Offset Correction Using Two-Mode Calibration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-resolution SAR ADCs face power inefficiency and accuracy limitations due to comparator offset errors, which are difficult to measure and correct, especially in high-resolution applications, leading to compromised conversion accuracy and increased power consumption.
Innovation Solution
A low-power, fully automated on-chip calibration method that detects and corrects comparator offset errors by utilizing a two-mode comparator and a programmable capacitor, allowing for direct error measurement and correction through an additional calibration cycle, thereby inducing a voltage step to counteract the offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a two-mode comparator is used to reduce power consumption, then power efficiency is improved, but dynamic offset error increases
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before normal ADC operation. A calibration mode is executed first to measure and compensate for comparator offset errors, ensuring that the offset is corrected before the comparator switches between low-power and high-precision modes during normal operation. This preliminary calibration eliminates dynamic offset errors that would otherwise degrade conversion accuracy.
Solution Approach 2:
The patent changes the comparator's resolution parameter dynamically by switching between two operating modes. In low-power mode, the comparator operates with reduced resolution to minimize power consumption, while in high-precision mode, full resolution is restored for accurate conversion. The calibration process measures the offset difference between these modes and applies compensation to maintain accuracy despite parameter changes.
2Measurement precision
If comparator resolution is increased for high-precision conversion, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent segments the conversion process into two distinct phases: calibration phase and normal operation phase. During calibration, the comparator operates in a dedicated calibration mode to measure offset errors. During normal operation, the comparator dynamically switches between low-power mode for most comparisons and high-precision mode only when needed, based on the calibration data. This segmentation allows the system to achieve high precision without continuously consuming high power.
Solution Approach 2:
The patent implements periodic calibration action where the comparator periodically switches between operating modes during the conversion process. The calibration is performed periodically to update offset compensation values, and during normal operation, the comparator periodically alternates between low-power and high-precision modes based on the conversion stage. This periodic action optimizes the balance between power consumption and measurement precision.
3Measurement precision
If off-chip calibration is implemented to correct comparator offset, then measurement precision is improved, but device complexity and power overhead increase
Solution Approach 1:
The patent merges the calibration function with the normal ADC operation by integrating the calibration circuitry within the ADC chip itself. The calibration mode shares common components with normal operation, including the comparator, DAC, and control logic. This merging eliminates the need for separate off-chip calibration equipment and reduces overall system complexity while maintaining the ability to correct comparator offset errors.
Solution Approach 2:
The patent implements self-service calibration where the ADC performs its own offset calibration without requiring external calibration equipment or manual intervention. The calibration mode is activated automatically, and the measured offset values are stored in on-chip memory for automatic compensation during normal operation. This self-calibration capability reduces device complexity and eliminates the need for external calibration resources.
Data Source
Figure 1~3
Figure 4~6
Figure 7~8
AI summary
The present invention relates to a method for calibrating an analog-to-digital converter, ADC, converting an input voltage signal into a digital output signal representing said input voltage signal. The method comprises : - sampling the input voltage signal applied to the analog-to-digital converter, - comparing the sampled input voltage signal with an output signal of a feedback digital-to-analogue converter, DAC, - determining in a search logic block of the ADC a digital code representation for the comparison result, -- performing a calibration by : performing an additional cycle wherein the last comparison carried out for determining the least significant bit of said digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode used in at least said last comparison, so obtaining an additional comparison, determining from the difference between the results of said additional comparison and said last comparison the sign of a comparator offset error between said first and said second comparator resolution mode, tuning, in accordance with said sign of said comparator offset error, a programmable capacitor (Ccal1) connected at the input of said comparator, thereby inducing a voltage step to counteract said comparator offset error.