ADC Front-End System Using Concurrent Capacitive Sampling
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) front-end systems require significant power and introduce noise due to the use of fast-settling buffers and frequency-selective loads, and they often occupy larger form factors, limiting their efficiency and performance in converting radio frequency (RF) signals to digital outputs.
Innovation Solution
The ADC front-end system employs a digital step attenuator (DSA) coupled with a sampling system that includes two sampling capacitors and switches, allowing concurrent sampling and charge redistribution between the capacitors, thereby eliminating the need for fast-settling buffers and frequency-selective loads, and controlling bandwidth through selective activation times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fast-settling buffers and frequency-selective loads are used in ADC front-end systems, then signal conversion accuracy is improved, but power consumption increases and noise is introduced
Solution Approach 1:
The patent removes fast-settling buffers and frequency-selective loads from the ADC front-end system. By extracting these power-consuming components and replacing them with a capacitive sampling network, the system achieves signal conversion without the associated power consumption and noise generation, while maintaining measurement precision through direct capacitive sampling of the analog signal.
Solution Approach 2:
The patent employs simple sampling capacitors and switches that are activated only during the sampling interval. These temporary, low-cost elements replace the expensive and power-hungry fast-settling buffers, providing sufficient signal conversion accuracy only when needed during the sampling phase, thereby reducing overall power consumption while maintaining measurement precision.
2Measurement precision
If fast-settling buffers and frequency-selective loads are used in ADC front-end systems, then signal conversion accuracy is improved, but noise is introduced
Solution Approach 1:
The patent extracts and eliminates fast-settling buffers and frequency-selective loads that generate noise during operation. By replacing them with passive sampling capacitors and controlled switches, the system achieves signal conversion accuracy without introducing the broadband noise and distortion associated with active buffer circuits and frequency-selective loading networks.
Solution Approach 2:
The patent uses simple sampling capacitors and switches that are activated only during the sampling interval. These temporary, low-noise elements replace the noisy fast-settling buffers, providing sufficient signal conversion accuracy only when needed during the sampling phase, thereby reducing overall noise while maintaining measurement precision.
3Productivity
If traditional ADC front-end components are used, then signal conversion is achieved, but device area increases
Solution Approach 1:
The patent merges the functions of fast-settling buffers, frequency-selective loads, and sampling circuits into a single integrated capacitive sampling network. By combining these previously separate components into one compact structure using sampling capacitors and switches, the system maintains signal conversion capability while significantly reducing the device area occupied by the ADC front-end.
Solution Approach 2:
The sampling capacitors and switches in the patent serve multiple functions simultaneously: they perform signal sampling, replace the function of fast-settling buffers, and eliminate the need for frequency-selective loads. This multi-functionality allows the system to maintain signal conversion capability while occupying less device area, as one compact circuit structure performs the work of multiple separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, noise, and form factor while maintaining efficient sampling and conversion of RF signals to digital outputs, providing a more efficient and compact solution compared to traditional ADC systems.
Implementation Method 1
The sampling system can be configured to sample an analog signal current provided from the DSA on the first sampling capacitor and the second sampling capacitor concurrently in response to activation of the at least one sampling switch to integrate the analog signal current as a sampling voltage on both the first and second sampling capacitors
Data Source
AI summary
One example includes an analog-to-digital converter (ADC) front-end system. The system includes a digital step attenuator (DSA) having an input and an output. The system also includes a sampling system having an input coupled to the output of the DSA. The sampling system includes a first sampling capacitor, a second sampling capacitor, and at least one sampling switch. The sampling system can be configured to sample an analog signal current provided from the DSA on the first sampling capacitor and the second sampling capacitor concurrently in response to activation of the at least one sampling switch to integrate the analog signal current as a sampling voltage on both the first and second sampling capacitors. The system further includes an ADC having an input and an output, the input of the ADC coupled to the output of the sampling system.