Image Sensor ADC Count Code Transfer to Reduce Peak Current
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Solution Overview
Problem
CMOS image sensors experience peak current issues during multi-bit toggling, leading to deteriorated pixel data quality and system abnormalities, which existing techniques have not adequately addressed.
Innovation Solution
An analog-digital converter with a count code generator, latch, operating circuit, and transfer controller, along with a comparator and counter, is used to manage pixel signals and reference signals, controlling the transfer of count codes based on clock signals to prevent peak current spikes and maintain data quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-bit toggling is performed during counting operation, then counting speed is improved, but peak current increases causing pixel data quality deterioration
Solution Approach 1:
The counting operation is divided into multiple sub-counting operations, where each sub-counter counts a portion of the total frames. This segmentation allows the counting to be distributed across multiple smaller units rather than one large counter, reducing the peak current demand while maintaining the overall counting capability and speed.
Solution Approach 2:
The patent dynamically adjusts the counting operation by enabling or disabling specific sub-counters based on the current frame count and total frame requirements. This dynamic control optimizes the counting process to maintain high speed while avoiding excessive peak current by activating only the necessary sub-counters at any given time.
2Productivity
If counting operation is continuously performed, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by dividing the continuous counting operation into periodic sub-counting cycles. Each sub-counter operates for a specific period (subset of frames) and then is disabled, allowing other sub-counters to take over. This periodic activation pattern maintains continuous counting productivity while reducing overall power consumption compared to keeping a single counter continuously active.
Solution Approach 2:
The patent discards the operation of individual sub-counters after they have completed their designated frame range, and recovers by activating different sub-counters for subsequent frame ranges. This approach allows the system to maintain continuous counting functionality while minimizing power consumption by ensuring that not all counting resources are active simultaneously.
3Speed
If count code is continuously transferred to operating circuit, then data processing speed is improved, but peak current occurs during transfer
Solution Approach 1:
The count code transfer is segmented into multiple smaller transfers corresponding to each sub-counter's frame range. Instead of transferring all count codes in one large operation that would cause peak current, the system transfers count codes from individual sub-counters in smaller, distributed batches, maintaining data processing speed while reducing peak current demand.
Solution Approach 2:
The patent applies partial action by transferring only the necessary portion of count codes from each sub-counter at appropriate times, rather than transferring all data at once. This partial transfer approach maintains adequate data processing speed by keeping data flow continuous while avoiding the peak current that would result from a single large transfer operation.
Data Source
AI summary
An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.