ADC Counter Synchronization to Prevent Image Sensor Code Skipping
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Solution Overview
Problem
Conventional CMOS image sensors experience code skipping in decoding due to differences in delay times between high-order and low-order bit counters, leading to inaccuracies in data conversion.
Innovation Solution
An analog-to-digital converter is designed with a comparator, low-order bit latch unit, high-order bit counter unit, and signal processing unit that detects and corrects code skipping by comparing low-order bit decoding signals with high-order bit values, ensuring synchronized counting and accurate digital signal conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate counting circuits are used for high-order and low-order bits, then circuit optimization and current consumption reduction are achieved, but delay time differences occur between counters causing code skipping
Solution Approach 1:
The patent implements a feedback mechanism where the stop signal from the low-order bit counter is fed back to the high-order bit counter to synchronize their operation. This feedback loop ensures that both counters stop at the same time, preventing code skipping while maintaining the separate counter architecture for low power consumption.
Solution Approach 2:
The patent introduces an intermediary stop signal that acts as a mediator between the low-order bit counter and the high-order bit counter. This intermediary signal coordinates the stopping of both counters, ensuring they finalize their counting simultaneously without requiring a unified counter circuit, thus maintaining energy efficiency while improving reliability.
2Area of stationary object
If separate counting circuits are used for high-order and low-order bits, then circuit area is reduced, but delay time differences cause code skipping in decoding
Solution Approach 1:
The feedback mechanism uses the stop signal from the low-order bit counter to control the high-order bit counter, creating a synchronized operation that prevents code skipping. This maintains the separate counter circuits for area efficiency while ensuring decoding accuracy through the feedback coordination.
Solution Approach 2:
The stop signal acts as an intermediary that coordinates between the separate high-order and low-order bit counters, enabling them to operate independently for area efficiency while ensuring they stop simultaneously for decoding accuracy.
3Productivity
If counters stop at different times, then individual counter optimization is achieved, but code skipping occurs during decoding
Solution Approach 1:
The feedback mechanism allows each counter to operate at its own optimized speed while the stop signal from the low-order bit counter feeds back to halt the high-order bit counter at the appropriate moment, ensuring both finalize simultaneously for data accuracy without compromising counting speed optimization.
Solution Approach 2:
The low-order bit counter completes its counting first (preliminary action) and generates a stop signal that then halts the high-order bit counter, ensuring both counters finalize their operation at the same time. This preliminary action approach maintains counting speed while ensuring data accuracy.
Data Source
AI summary
[Object] To prevent code skipping in decoding.[Solution] Included are a low-order bit latch unit (63) that latches digital code data as a low-order bit, a high-order bit counter unit (64) that counts one or both of edges of a control signal corresponding to a reference clock, and stops counting of high-order bits, triggered by output of a comparator (62) being inverted, a low-order bit decoding signal latch unit (65) that latches a low-order bit decoding signal, and a signal processing unit (8).